Hironori Kasahara, Waseda University, Japan


OSCAR Compiler for Automatic Parallelization and Power Reduction for Multicores and Manycores


Multicore processors have been attracting much attention in wide variety of fields, such as smart phones, tablet computers, cameras, games, PCs, robots, medical systems, cloud servers and supercomputers, to attain both high performance and low power. This talk introduces the OSCAR (Optimally Scheduled Advanced Multiprocessor) compiler for automatic parallelization and power reduction for multicores and manycores. The compiler allows us automatic parallelization and power reduction of a sequential C or Fortran program for any number of processor cores on homogeneous and heterogeneous multicores with the original compilation techniques, such as multigrain parallelization combining hierarchical coarse grain task parallelization, loop parallelization and statement level fine grain parallelization, global cache or local memory optimization, data transfer overlapping using DMA, power reduction using DVFS and power gating for each cores. Also, the compiler can generate portable parallel codes using OSCAR API for various homogeneous and heterogeneous multicores. The performance has been evaluated for multimedia, medical, automobile, scientific applications on various multiprocessor systems based on Renesas’s (SuperH and V850), Fujitsu’s (FRV and SPARC), ARM’s, Intel’s, AMD’s and IBM’s processor cores.


Dr. Hironori Kasahara is a Professor at Department of Computer Science and Engineering and Director of Advanced Multicore Processor Research Institute, Waseda University, Tokyo, Japan and a member of IEEE Computer Society Board of Governors. He received a Ph.D. degree from Waseda University in 1985, and was a visiting scholar in the University of California at Berkeley in 1985, a fulltime assistant professor in 1986, associate professor in 1988 and professor in 1997 at Waseda University. Also, he was a visiting researcher at the University of Illinois at Urbana-Champaign, Center for Supercomputing R&D in 1989-90. He led several Japanese National Projects such as METI/NEDO “Advanced Parallelizing Compiler”, “Multicore for Real-time Consumer Electronics”, “Leading Research for Low Power Manycores” and “Green Computing Systems R&D”. He served as a member of MEXT Earth Simulator Architecture Advisory Board, Next Generation Supercomputer Evaluation Committee, High Performance Computing Infrastructure Committee and so on. His academic activities include 189 reviewed papers, 104 invited talks, 29 symposium papers, 134 technical reports, 154 Annual Convention Papers, 32 patents and 443 articles of news papers, TV, magazines, web news and so on. Also, he has served as a PC chair, a PC or a Publication Chair of many conferences supported by IEEE, ACM, IPSJ, such as SC, ICS, ASPLOS, PPoPP, ICPP, IPDPS, ICPADS, CONPAR, JSPP, LCPC and so on. He has received the IFAC World Congress Young Author Prize, the IPSJ Sakai Special Research Award, the Grand Prix runner-up prize at the 2008 LSI of the Year, Best Research Award at the Intel Asia Academic Forum and IEEE Computer Society Golden Core Member. His research interests include parallelizing compilers, multicore and manycore architectures, and their application to consumer electronics like smart phones, automobiles, medical systems and supercomputers.

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