Yukoh Matsumoto, TOPS Systems Corp., Japan


Distributed Processing Heterogeneous Multicore / Manycore / 3D Multichip SoC with Zero-Overhead Message Passing and Stream Processing HW/SW mechanism


For embedded systems, Distributed Processing is one of major approaches for implementing heterogeneous hardwired logic blocks on SoCs because of its advantages such as performance per cost, easiness of integration, scheduling, and synchronization of multiple functions. Instead of hardwired logic based SoCs, for higher flexibility and scalability, Multicore, Manycore, or even as a 3D stacked Multichip based SoCs are expected to replace them. However, overhead of message passing between processor cores such as extra-processor cycles as well as energy for communication and synchronization through message passing FIFO access between processes is one of bottlenecks for energy-efficient processing. This presentation introduces mechanisms for Zero-Overhead Message Passing between processes and Stream Processing on each process. This technique is applied to three types of SoCs; 1) Ultra-Android software platform on a heterogeneous Multicore processor, 2) Video mining applications on Manycore processor, 3) Image and Video processing on 3D chip stacking heterogeneous Multicore on Multichip. The Zero-Overhead Message Passing can hide processor cycles required to execute 100’s of instructions for accessing FIFOs and synchronizing execution of processes. The Zero-Overhead Message Passing is implemented with pre-fix instructions for event based synchronization, event counters, FIFO configuration registers, event network between processors, and FIFO. FIFO can be implemented on a memory or on a shared register bank between cores. In addition, the FIFO access is scheduled as Stream Processing with block load/store instructions, and executed in parallel with regular instructions in each processor core’s instruction execution pipeline. As the reults, Message Passing consumes zero processor cycles when it does not have to wait for synchronization, and needs no bus and memory access when a message is passed through a shared register bank. These increase energy-efficiency of distributed processing on microprocessor based SoCs while keeping its flexibility and scalability.


Dr. Yukoh Matsumoto is the chief architect, and president and CEO of TOPS Systems Corp. He led “Cool System : Ultra-Low-Power 3D stacked heterogeneous Multicore / Multichip” project supported by NEDO and “Ultra-Android : Distributed Processing embedded software platform” project supported by METI. Currently, he is working on “Low-Power Many-Core Architecture and Compiler Technology” project supported by NEDO. In his 26 years of carrier, he has architected and designed over 10 advanced microprocessors such as, Embedded Multicore processors, x86 microprocessors, and DSPs. He funded TOPS Systems Corp. in 1999, and received the Takeda Techno-Entrepreneurship Award, Tsukuba Venture Award, and ET Award in hardware in 2001, 2010, and 2011 respectively. Prior to TOPS Systems, he has held several positions within Texas Instruments and its Research and Development organization in US and Japan, and within V.M. Technology, a microprocessor start-up in Japan. He received the Dr. of Information Sciences (the Ph.D.) degree from the Graduate School of Tohoku University, Sendai, Japan, in 2007, and participated in the MOT (Management of Technology) program at the Graduate School of Engineering in Tokyo University from 2004 through 2005.

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