Benjamin Carrion Schafer, NEC Corporation, Japan
Kazutoshi Wakabayash, NEC Corporation, Japan


HW/SW Co-simulation integration into HLS flow


This work presents the integration of a HW/SW co-simulation and co-debugging environment into a High Level Synthesis (HLS) flow. We show how transaction based SW simulation can be co-simulated with cycle accurate HW models through transactors and how these can be debugged together with a HW source code debugger. This debugger allows the timing verification of synthesizable ANSI C and SystemC. Results show that this method allows a fast and easy way to fully verify complete SoC designs.


Benjamin Carrion Schafer received the B.Eng. degree in electrical engineering from the Polytechnic University of Madrid, Madrid, Spain, the M.Sc. degree in microelectronics from Birmingham City University, Birmingham, U.K., and FH-Darmstadt, Darmstadt, Germany. After completing his Ph.D. at the University of Birmingham, he was a Postdoctoral Researcher with the Computer Science Department at the University of California Los Angeles (UCLA), from 2003 to 2004. He was a Visiting Researcher at Seoul National University, Seoul, Korea, from 2005 to 2007 at the School of Electrical Engineering and Computer Science. Currently, he works as an Assistant Research Manager at NEC Corporation's Central R&D Laboratories, System IP Core Department, Design Methodology Group in Kawasaki, Japan. Dr. Carrion Schafer has been engaged in the research and development of VLSI systems, reconfigurable computing, thermal-aware VLSI design and High Level Synthesis (HLS). He served on the TPC of CASES 2006 and as a committee member at the RECONFIG, DAC (user track) and ESLSyn conferences. He is also member of OSCI’s (Accellera) SystemC synthesizable user group committee.

Kazutoshi Wakabayashi received his B.E. and M.E. degrees and Dr. of Engineering from the University of Tokyo in 1984 and 1986. He was a visiting researcher at Stanford University during 1993 and 1994. He joined NEC Corporation in Kawasaki Japan in 1986 and he is currently a senior research manager of the EDA R&D Center, Central Research Laboratories. Dr. Wakabayashi has been engaged in the research and development of VLSI, CAD systems; high-level and logic synthesis, formal and semi-formal verification, system-level simulation, HDL, emulation, HLS and floorplan links, and reconfigurable computing. He served on executive committee or organizing committee of some international conference including: ASP-DAC'09 General Chair, CODES+ISSS'09 Co-Technical Program Chair. A Secretary of Steering Committee of ASP DAC, and Asian Rep. of ICCAD, Asian Rep. of DAC, Tutorial Chair of ASP DAC 2006, He has served on the program committees for several international conferences including: DAC, ICCAD, DATE, ASP-DAC, ISSUS,SASIMI, and ITC-CSCC, ISCAS, VLSI-TSI and SBCCI. Also, he has served as a general chair, a secretary, and a Technical Program Committee member for a number of Japanese conferences,including: Institute of Electronics, Information and Communication Engineers of Japan (IEICE), the Information Processing Society of Japan (IPSJ), System LSI WS, Karuizawa WS. He is currently chair of SIG on VLSI design methodology of IEICE, and elected member of IEICE. He was an associate editor of Transactions on IEICE on VLSI CAD, DAEM. He is a rep. of CEDA (Council for EDA) of IEEE. He is also a member of IEEE, IPSJ, and IEICE. He received the Yamazaki-Teiichi Prize in 2004, and the IPSJ Convention Award in 1988, Sakai Kinen Special Award in 2001, and the NEC Distinguished Contribution Award in 1993 for his logic synthesis system, in 1999 for his formal verification and in 2006 for his High Level Synthesis system. His C-based Synthesis and Verification tool suite called "CybeWorkBench" received a Grand prize of "LSI of the Year 2003" and "LSI of the Year 2007".

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