Kees Vissers, Xilinx, USA


Trends in FPGA systems and Programming


The FPGA technology has seen an amazing scaling, tracking the best of the ITRS roadmap. When this is put in the context of the roadmap of image processing requirements there is a good match. Conventional 1920 x 1080 HDTV at 60 frames per second, often called 1080p60 HDTV, has a sample rate in the range of 150Msamples/sec. The new 4k x 2k standards at 60frames per second is 8 times this sample rate. When a video program has in the range of a 1000 operations per pixel the compute requirements are then ranging from 150Gops to 1200Gops. In this talk we show that the combination of modern ARM based A9 processors combined with an affordable amount of FPGA fabric can achieve the compute requirements for modern video processing. We will show the C/C++ programs for a simple Sobel Filter at HDTV rate, that are the input for High-Level Synthesis based programming of these FPGAs. We will show the performance results of using this methodology in medical applications using floating point, that leverages the tight integration of processors and accelerators via the caches. The complete system consists of AXI based DMA subsystems, dedicated accelerators and linux based processor subsystems.


Kees Vissers graduated from Delft University in the Netherlands. He worked at Philips Research in Eindhoven, the Netherlands, for many years. The work included Digital Video system design, HW –SW co-design, VLIW processor design and dedicated video processors. He was a visiting industrial fellow at Carnegie Mellon University, where he worked on early High Level Synthesis tools. He was a visiting industrial fellow at UC Berkeley where he worked on several models of computation and dataflow computing. He was a director of architecture at Trimedia, and CTO at Chameleon Systems. Today he is heading a small team of researchers at Xilinx. The research topics include next generation programming environments for processors and FPGA fabric, high-performance video systems, wireless applications and new datacenter applications. He is also involved in applications and performance analysis of new memory architectures for the combination of closely integrated FPGA and memory technology.

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