Christian Weis, TU Kaiserslautern, Germany


Sliced & Packed: Co-optimization of 3D stacked DRAM and Controller


3D integration of chips offers a unique opportunity to stack heterogeneous technologies, like DRAM and logic. Mobile SoC platforms are rapidly evolving towards heterogeneous Many-Core architectures, with staggering main memory bandwidth requirements. 3D-integrated WIDE-IO DRAM is today one of the most appealing options to obtain bandwidth at an acceptable power/area cost, but it's no silver bullet. In this talk we will discuss our approach to re-architect vertically stacked memories, their controller and interfaces to logic SoCs, and we will highlight opportunities for improving memory organization and the co-optimization of 3D-DRAMs and memory controller.


Christian Weis received the Diploma degree in Electrical Engineering from the University of Kaiserslautern, Germany, in 1996. From 1996 to 1998 he was employed at Mitsubishi Semiconductor Europe, Germany, where he was engaged in the development of microcontrollers. From 1998 to 2009, he worked at Siemens Semiconductor, Infineon Technologies and Qimonda, Munich, Germany, in DRAM design. During this time frame he was involved in DRAM design for graphics and commodity DRAM products. From 2006 he was design team leader for the 1Gb DDR3 DRAM, the first DDR3 volume product at Infineon/Qimonda. In 2009, he joined the Microelectronic Systems Design Research Group, Kaiserslautern, Germany, and his research interests are the exploration and optimization of DRAM-subsystems in 3D integrated MPSoCs. He holds several patents related to DRAMs and DRAM design.

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