Slides available here!

Speaker:

Charlie Janac, Arteris, USA

Title:

Heterogeneous, Distributed and Scalable cache-coherent interconnect

Abstract:

Multiprocessor SoCs require hardware cache coherency in order to simplify their programming, but this hardware can cause IP integration, timing closure and performance issues. This talk discusses a novel highly configurable cache coherent interconnect that accommodates multiple heterogeneous caching agents, snoop filters, proxy caches ("IO caches"), and clock and voltage domains in a scalable distributed architecture that eases physical implementation and timing closure. This interconnect IP has been optimized for heterogeneous cache coherent systems and employs configurable proxy caches that increase the performance of non-coherent agents accessing the coherent subsystem.

Bio:

K. Charles Janac is the Chairman, President and Chief Executive Officer of Arteris Inc.. Arteris has pioneered the market for use of Network on Chip (NoC) interconnect IP and Tools for on-chip communications in semiconductor chips. Arteris products are designed into some of the highest volume SoCs being delivered today by over 61 semiconductor companies.

Charlie has nearly 30 years of experience building technology companies. He started his technology career as employee number two of Cadence Design Systems (originally SDA Inc.), a publicly traded EDA software company. Subsequently, he served as President/CEO of HLD Systems, Smart Machines and Nanomix. Charlie also served as Entrepreneur-in-Residence at Infinity Capital, an early stage venture capital firm in Palo Alto, California.

Born in Prague, Czech Republic, he holds both a B.S. and M.S. degrees in Organic Chemistry from Tufts University and an MBA from Stanford Graduate School of Business. Charlie, his wife Lydia, reside in Los Altos Hills, California.



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