Slides available here!

Speaker:

Fabien Clermidy, CAE-LETI, France

Title:

3D multicore: from WIDEIO to photonic interposers

Abstract:

As 3D integration is now largely used in the development of memories (3D Flash, 3D DRAM such as HBM, WIDEIO or HMC), it has not yet been adopted by SoC designers. However, the trend to divide big SoCs in smaller pieces, called chiplets, is on-going: at ISSCC'15, MARVELL announced that designing complex SoC is becoming more and more difficult, due to the following reasons:

- Extremely dynamic market: volume is fragmented, the window to launch a new product is hard to forecast with precision.

- Design complexity is increasing drastically: for power efficiency reason, heterogeneous tiles are integrated adding to the complexity. Thus design cycles are longer.

- Process complexity is increasing: time to production gets longer thus time to market is less predictable.

Marvell then proposes the concept of "Modular Chip" or MoChi, a Lego-like concept relying on the concept of Virtual SoC and advanced 3D integration. As a result, 3D is no more seen as an "advanced packaging" option but rather as a technology allowing new concepts of products developments which will be easier, less costly and more dedicated.

In this presentation, we will show how 3D integration technologies can help developing this new concept through different 3D integration prototypes developed at CEA: starting from WIDEIO DRAM integration, we will explore the 3D NOC concept and then what an active interposer can bring as an added value to this concept. Finally, some perspective on photonic interposer will be presented.

Bio:

Fabien Clermidy obtained his master degree in 1994, his Ph.D in Engineering Science from INPG, Grenoble in 1999 and his supervisor degree (Habilitation a Diriger les Recherches) from INPG in 2011.

Fabien is a pioneer in designing Network-on-Chip based multi-core and was one of the architects of the first asynchronous-based Network-on-Chip published at ISSCC in 2007. He then took the lead of the second generation of Network-on-Chip based multicore dedicated to 3GPP-LTE and was the leader of the CEA team which has been working on the P2012 multi-core architecture in collaboration with STMicroelectronics and ST-Ericsson. At this period, his team elaborated one of the first 3D multi-core prototypes embedding a WIDE-IO DRAM memory called WIOMING.

Fabien is currently head of the digital design laboratory at CEA-LETI working on multi-core architectures and ultra-low-power devices with a focus on emerging technologies. In this position, he manages a team implied in the development of new architectures using emerging technologies such as 3D TSV, 3D monolithic integration and emerging memories such as RRAM.

Fabien has published 2 books, more than 75 journal and conferences papers and is author or co-author of 15 patents.



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