Slides available here!

Speaker:

Shinya Takamaeda, Nara Institute of Science and Technology, Japan

Title:

Customizable Hardware Abstraction

Abstract:

How do you design and implement a custom hardware? We usually use HDL (hardware description language), such as Verilog HDL and VHDL, to explicitly express a hardware structure in detail. However, HDL-based hardware development requires a huge effort due to its low expression ability, even by expert hardware designers. Other modern alternative is to use a high-level synthesis tool that enables users can express hardware behavior by using a programming language, such as C and OpenCL. It certainly improves productivity of hardware development. However, we cannot control perfectly how the compiler generates a hardware structure as the result. In order to maximize the hardware performance with a sufficient productivity, we explore a novel approach that allows users to build up a custom abstraction of hardware for each purpose. In this talk, we present Veriloggen, an explicit and high-level hardware modeling DSL on Python which is a major and powerful script language. Veriloggen first provides a fundamental abstraction of Verilog HDL. Then users can construct their own higher level abstraction as an explicit design pattern by utilizing the entire language features of Python. Therefore, Veriloggen provides both cutomizability and productivity of custom hardware development.

Bio:

Shinya Takamaeda received the B.E, M.E, and D.E degrees from Tokyo Institute of Technology, Japan in 2009, 2011, and 2014 respectively. From 2011 to 2014, he was a JSPS research fellow (DC1). Since 2014, he has been an assistant professor of the Graduate School of Information Science, Nara Institute of Science and Technology, Japan. His research interests include FPGA computing, high level synthesis, memory system, and processor architecture. He is a member of IEEE, IEICE, and IPSJ.



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