Slides available here!

Speaker:

Zining Wu, Marvell, USA

Title:

Design challenges in the "More-than-Moore" Era

Abstract:

In recent years, several growth engines have fueled semiconductor industry - the proliferation of personal mobile devices, the onset of IoT revolution, and the new business opportunities brought up by Big Data and cloud services. In the meantime, a "slow-down" of Moore's law is felt throughout the industry, where moving to smaller geometry takes longer time and requires more investment. The conflicting trends between higher development and production cost and increasingly segmented market require semiconductor companies to offer "More-than-Moore" advances in technologies, and to be more nimble than ever in product development.

In this talk, we discuss changes needed in design methodology to address the "More-than-Moore" challenges. We will show how recent advancement in simulation, verification, and emulation can help us shorten design cycles and improve quality. We will also show that by co-developing software and hardware, we can "shift left" semiconductor design cycles. To address production cost challenges, we will introduce the concept of Virtual SOC, where we no longer integrate all the functions into a monolithic SOC chip. Instead, we pre-make functional modules, and assemble them through pre-defined, low power inter-chip interconnects to achieve the same performance as multi-core SOCs.

Bio:

Dr. Zining Wu serves as Chief Technology Officer of Marvell Technology Group Ltd., a position he has held since January 2014. In this role, Dr. Wu is responsible for overseeing all technical aspects of the company including establishing the company's technical vision and strategic innovation initiatives, and directing R&D project execution and future growth.

Prior to his current position, Dr. Wu was Vice President, Data Storage Technology at Marvell. In this role, he was responsible for leading the engineering group that delivers innovative storage technologies for the hard disk drive and SSD electronics markets. During his leadership, Marvell announced the world's first low-density parity-check (LDPC) code based SSD controller that more than triples the reliability of NAND flash; the first native PCIe SSD controller for modular scalability, raising the bar in data storage by delivering an unprecedented level of I/O performance; and the world's first NVRAM-powered PCIe SSD cache solution providing industry-leading performance for cloud computing data centers. Previous to this role, Dr. Wu held various engineering and managerial roles within Marvell, including Vice President of Engineering for wireless communication SoCs, where his team delivered the industry's best-in-class 802.11ac chips.

Dr. Wu holds a Bachelor of Science degree in Electronic Engineering from Tsinghua University in Beijing, China, and a Master of Science degree and Ph.D. in Electrical Engineering from Stanford University.



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