Masaaki Kondo
The University of Tokyo, Japan
A Design of Scalable Deep Neural Network Accelerator Cores with 3D Integration
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As edge computing is becoming one of the hot topics in many research fields, many Deep Neural Network (DNN) applications are expected to run on mobile embedded systems. Developing high-performance and power-efficient DNN engines becomes one of the important challenges for embedded systems. Since DNN algorithms or network models are frequently updated, flexibility and performance scalability to deal with various types of networks are crucial requirement of the DNN accelerator design. In this talk, we present the architecture and LSI design of a flexible and scalable CNN accelerator called SNACC (Scalable Neural Acceleration Cores with Cubic Integration) which consists of several processing cores, on-chip memory modules, and ThruChip Interface (TCI). We also present preliminary evaluation results on its power efficiency with a prototype LSI.
Biography
Masaaki Kondo received the B.E. degree in College of Information Sciences and the M.E degree in Doctoral Program in Engineering from University of Tsukuba in 1998 and 2000 respectively, and the Ph.D. degree in Graduate School of Engineering from the University of Tokyo in 2003. He is currently an associate professor in the Graduate School of Information Science and Technology at the University of Tokyo. His research interests include computer architectures, high-performance computing, and cognitive computing.