Tohru Ishihara
Nagoya University, Japan
Near-Threshold Cache Architecture for Ultra-Low Energy Computing
Download SlidesAbstract
Near-threshold computing is one of the most promising approaches for high-performance and energy efficient design of microprocessors. However, it is still challenging for on-chip caches to use near-threshold voltage because of their high sensitivity to noises and process variations. In this talk, as a remedy to those issues, we introduce a near-threshold standard-cell memory (NT-SCM) which is constructed based on standard-cell latches and can be stably operating with near-threshold supply voltage. We also introduce a hybrid 2-level cache subsystem which is constructed with a normal L1 cache and a NT-SCM-based tiny L0 cache located between CPU core and the L1 cache. With the simulation results using RISC-V processor integrating the hybrid 2-level cache on a chip, we show the effectiveness of the hybrid 2-level cache subsystem over existing on-chip cache subsystems.
Biography
Tohru Ishihara received his Dr.Eng. degree in computer science from Kyushu University in 2000. For the next three years, he was a Research Associate in the University of Tokyo. From 2003 to 2005, he was with Fujitsu Laboratories of America as a Research Staff of an Advanced CAD Technology Group. From 2005 to 2011, he was with Kyushu University as an Associate Professor. For the next seven years he was with Kyoto University. In October 2018, he joined Nagoya University where he is currently a Professor in the Department of Computing and Software Systems. His research interests include low-power design methodologies and power management techniques for embedded systems. Dr. Ishihara is a member of the IEEE, ACM, IPSJ and IEICE.