Tsuyoshi Isshiki
Affiliation, Country
CNN Training HW Architecture Design Using C2RTL SoC Synthesis/Verification Framework
Download SlidesAbstract
In this talk, we introduce our recent works on C++-based system design framework (C2RTL) for CNN training HW architecture designs. Although there are vast amount of works in CNN inference HW architectures, CNN training HW architectures, aside from CPU/GPU-based platforms, have not been widely addressed. The entire design/verification process of CNN training HW, starting from FP32 (32-bit floating-point) algorithm description on C++ and algorithm refinement using dynamic fix-point arithmetic operations are carried out on our C2RTL framework in which the generated RTL with over 10M gates is fully synthesized from few hundred lines of C++ codes.
Biography
Tsuyoshi Isshiki has received B.E. and M.E. degrees from Tokyo Institute of Technology in 1990 and 1992, respectively, and received PhD in Computer Engineering from University of California at Santa Cruz in 1996. He is currently a professor at Tokyo Institute of Technology, Global Scientific Information and Computing Center. His research interests include multimedia SoC designs, Multiprocessor SoC design methodology/tools and deep learning HW accelerator synthesis.