Frédéric Pétrot

Grenoble University, France

Simulation and code generation for the 128-bit RISC-V ISA

Abstract

The widespread adoption of 64-bit processor architectures dates from the very beginning of the millennium, quickly followed in 2004 by the first multi-core consumer architectures. Although it seems unlikely that processors with 128-bit addresses will be needed in the near future, extrapolating the growth of memory in computing centers indicates that a 65th bit of address may be needed in the 2030s. This presentation sets the stage by focusing on the tooling needed to design and test these architectures, through a simulator and cross-development tools.

Biography

Frederic Petrot received the PhD degree in Computer Science from Universite Pierre et Marie Curie (Paris VI), Paris, France, in 1994, where has been Assistant Professor in Computer Science until September 2004. He joined TIMA in September 2004, where he holds a professor position at Grenoble Institute of Technology, France. His research interests are in multiprocessor systems on chip architectures, including circuits and software aspects, and CAD tools for the design and evaluation of hardware/software systems. He currently holds the Digital Hardware AI Architectures chair of Grenoble Multidisciplinary Institute in Artificial Intelligence.