Iris Bahar

Colorado School of Mines

Concurrent Data Structures with Near-Memory Processing

Abstract

In recent years, there has been a renewed interest in near-memory processing (NMP) architectures as a workaround for the performance and energy issues of frequent and irregular memory accesses. However, effective use of NMP architectures requires rethinking data structures and their algorithms. We focus on cache-optimized data structures, such as skiplists and B+ trees, often used in online transaction processing (OLTP) systems to enable fast key-based lookups. We provide a HW-SW co-design solution of NMP-aware algorithms for these concurrent data structures and show that our approach can improve performance by more than 2X compared to the state-of-the-art.

Biography

R. Iris Bahar received the B.S. and M.S. degrees in computer engineering from the University of Illinois, Urbana-Champaign, and the Ph.D. degree in electrical and computer engineering from the University of Colorado, Boulder. She recently joined the faculty at the Colorado School of Mines in January 2022 and serves at Department Head of Computer Science. Before joining Mines, she was on the faculty at Brown University for 26 years and held dual appointments as Professor of Engineering and Professor of Computer Science. Her research interests focus on energy-efficient and reliable computing, from the system level to device level. Most recently this includes the design of robotics systems. She is the 2019 recipient of the Marie R. Pistilli Women in Engineering Achievement Award and the Brown University School of Engineering Award for Excellence in Teaching in Engineering, as well as the 2022 recipient of the University of Illinois ECE Distinguished Alumni Award. She is an IEEE fellow and an ACM Distinguished Scientist.