Tohru Ishihara

Nagoya University, Japan

A Standard-Cell-based DRAM for Fully Synthesizable Memory-Centric Accelerators Design

Abstract

Memory-centric computing is one of the most promising approaches for applications such as edge AI accelerators that require both high-performance and highly energy efficient processing. Since AI algorithms and their accelerator architectures are evolving rapidly, the biggest challenge in edge AI design is to rapidly synthesize high performance and highly energy efficient memory-centric hardware. In this talk, to address this challenge, we introduce a gain-cell based standard-cell memory (GC-SCM) which is constructed based on a gain-cell DRAM which is highly area efficient and fully logic compatible. In this talk, we share results of GC-SCM design.

Biography

Tohru Ishihara received his Dr.Eng. degree in computer science from Kyushu University in 2000. For the next three years, he was a Research Associate in the University of Tokyo. From 2003 to 2005, he was with Fujitsu Laboratories of America as a Research Staff of an Advanced CAD Technology Group. From 2005 to 2011, he was with Kyushu University as an Associate Professor. For the next seven years he was with Kyoto University. In October 2018, he joined Nagoya University where he is currently a Professor in the Department of Computing and Software Systems. His research interests include low-power design methodologies and power management techniques for embedded systems. Dr. Ishihara is a member of the IEEE, ACM, IPSJ and IEICE.