Tsuyoshi Isshiki

Tokyo Institute of Technology, Japan

RISC-V Embedded CNN Accelerator on C2RTL System-Level Design Verification Framework

Abstract

In this talk, we introduce our recent works on RISC-V embedded CNN accelerator using our C++ based system design framework (C2RTL). Utilizing our C++ RISC-V core model (RV32-IMAF) with cache/MMU and AXI4 master ports,
as well as the entire SoC models including AXI4 bus system and slave peripherals, we have developed a CNN accelerator engine embedded within the RISC-V processor pipeline, enabling a fully SW-defined low power CNN platform.
Our CNN accelerator contains 576 MAC units, 262GB/s high-bandwidth on-chip memory for sustaining 460 GOPs peak performance under 80mW, and 12.8GB/s DMAC for off-chip data transfer of feature maps and weights.

Biography

Tsuyoshi Isshiki has received B.E. and M.E. degrees from Tokyo Institute of Technology in 1990 and 1992, respectively, and received PhD in Computer Engineering from University of California at Santa Cruz in 1996. He is currently a professor at Tokyo Institute of Technology, Dept. Information and Communications Engineering. His research interests include multimedia SoC designs and RISC-V SoC design methodologies and tools.