Masato Motomura

Tokyo Institute of Technology, Japan

Exploring AI Computing Architectures Toward Future SoC

Abstract

Thanks to the tremendous advances and success of deep neural networks, computer architecture research has been booming and enjoying its “Golden Age” recently: a lot of architectural proposals have been proposed for the accelerated execution of “AI Computing”, whose central focus is to handle various forms of “explosions”: either in input data or output combinations. Most of them have common architectural features, i.e., hardware-oriented, reconfigurable, domain-specific, and in/near-memory.
This talk will try to provide insights on why they are happening and what are the recent findings by showcasing research activities from our group.

Biography

Masato Motomura received B.S. and M.S. in 1985 and 1987, respectively, and Ph.D. of Electrical Engineering in 1996, all from Kyoto University. He joined NEC research laboratories in 1987, where he worked on various hardware architectures including multi-thread parallel processors, memory-based processors, and reconfigurable systems. From 2001 to 2008 he led research and productization of DRP (dynamically reconfigurable processor) that he invented. He was also a visiting researcher at MIT Laboratory for Computer Science from 1991 to 1992. He became a professor at Hokkaido University in 2011, and then a professor at Tokyo Institute of Technology from 2019 where he is currently leading AI Computing Research Unit. He won the IEEE JSSC Best Paper Award in 1992, IPSJ Best Paper Award in 1999, IEICE Achievement Award in 2011, and ISSCC Silkroad Award as the last author in 2018, respectively. He is a member of IEICE, IPSJ, JSAI, and EAJ. He is an IEEE Fellow.