23 - 27 June 2008, Aachen, Germany
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PREVIOUS MPSoC - MPSoC'07 - MPSoC'06
- MPSoC'05
- MPSoC'04
- MPSoC'03
- MPSoC'02
- MPSoC'01 |
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MPSoC'08
Information: |
| MPSoC
Information: Ahmed Jerraya CEA-LETI, MINATEC 17 rue des Martyrs 38054, Grenoble, France Tel: +33 438 780 128 Fax: +33 438 785 182 E-mail: ahmed.jerraya(at)cea.fr |
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Web
Manager: |
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MPSoC-Flyer: |
MPSoC'08 Format
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Keynotes on key MPSoC trends.
Technical sessions to present strategic directions and state-of-the-art research. The program will be made of in-depth technology challenge presentations and educational panels made of short keynotes followed by discussions. All the presentations will be made by CTO-level speakers. The sessions will cover:
- MPSoC Architecture
- On-chip interconnect for heterogeneous and highly parallel MPSoC
- Memory architecture
- Nanotechnologies
- Networking
- MPSoC Applications Platforms
- Killer applications for MPSoC
- MPSoC platforms
- HW vs. SW reconfiguration
- Mixed signal
- MPSoC Programming
- Embedded RTOS
- Flexible CPU
- Parallel programming models
- MPSoC Design Methodologies
- Concurrent design
- HW-SW debug & verification
- Testing
- Case studies
- HW/SW interfaces codesign.
- MPSoC Architecture
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An executive half day session including presentations by top executives, investors and analysts to discuss challenges and opportunities for future SoC applications and technologies.