Speaker:

Paul Heysters, Recore systems, NL

Title:

About Many-cores, Reconfigurability and Reliability

Abstract:

Raw computation performance can be scaled enduringly by increasing the number of cores in a design. This replication strategy is encouraged by the shrinking of technology. Good scalability of the many-core architecture is key to cope with increasing design size and complexity. Unfortunately, with every technology generation, the reliability and variability (in terms of performance and power) increase. Reconfigurability combines programmability with efficiency. This tradeoff pays particularly off in the area of embedded streaming digital signal processing applications. Given the complexity of current applications, programmability is essential to develop (i.e. debug) future systems. Software development tools need be an integral part of any embedded many-core solution. Reconfigurable many-core systems can help improving reliability as the flexibility of such systems can be used for detecting, circumventing and/or correcting faulty parts, even at run-time.

Bio:

Dr. Paul M. Heysters is CEO and co-founder of Recore Systems. He has more than 8 years experience working in the field of reconfigurable computing. In his career, he has worked for high-technology companies in both Europe and the USA, including Ericsson, Philips and Chameleon Systems. Before joining Recore Systems, he conducted PhD. research on coarse-grained reconfigurable computing at the University of Twente (The Netherlands) and worked collaboratively with industry organizations. Paul is board member of the Dutch Shared EDA association. He is takes part in the steering committee of the European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC). He is a member of the coordination board of the Dutch Sensor Technology Applied in Reconfigurable Systems (STARS) project. Paul received his MSc degree in Computer Science from the University of Twente in 1998 and his doctorate in 2004 for his PhD thesis entitled “Coarse-Grained Reconfigurable Processors – Flexibility meets Efficiency.”



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