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Giorgio Cesana, ST, France


The FD-SOI Technology for Very High-speed and Energy Efficient SoCs


In a world which is more and more mobile, and with the expansion of connected objects, it is mandatory having semiconductor technologies and design techniques aimed to energy efficiency, still guaranteeing the required performances. FD-SOI (Fully Depleted Silicon On Insulator) is a planar semiconductor technology offering the advantages of fully depleted transistors from the 28nm technology node, joining the advantages of a general purpose high speed technology (speed, low dynamic power) with the ones of a low power technology (low leakage, simple). After a brief introduction to the technology and its peculiarities, the talk illustrates few applicative examples in the field of embedded multiprocessor SoC, such as high speed CPUs and GPUs, ultra-low voltage but fast cores, and IPs. The first example describes a dual core CPU subsystem, detailing its architecture for enabling DVFS and process compensation through body bias, showing silicon results obtained on 28nm FD-SOI and compared to a 28LP bulk technology implementation. The second example details ultra-low voltage design techniques exploiting some peculiarities of the FD-SOI technology, applied to a DSP; silicon results are also shown, showing the potential of body-bias for obtaining very high speeds in ultra-low voltage conditions.


Giorgio Cesana is Director of Marketing and Communication at the Technology R&D Group of STMicroelectronics (ST). He joined ST's Central R&D in Agrate, Italy in 1994, then moving to Crolles, France, in 2000. In 2009, he created the activity of Technology R&D Marketing. In this role, he determines market demand for future technology and design platforms, oversees dedicated technology developments, monitors industry trends in new technologies and provides PPA benchmarks. Currently, he is in charge of the marketing definition of the FD-SOI technologies of STMicroelectronics.

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