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Prof. Sorin Cotofana, Delft University of Technology, Netherlands


Ageing Assessment, Prediction, and Lifetime Reliability Aware Resource Management


With aggressive scaling of MOSFET technology for the past decades, reliability has becoming a rising concern both at design-time and runtime. Transistors suffer multiple degradation mechanisms during operation, e.g., Negative Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI). As a result, device performance degrades, due to these failure mechanisms, and eventually devices might fail during their expected lifetime. Moreover these failure mechanisms are combined with Process, Voltage, and Temperature (PVT) variations inside a chip, which make lifetime reliability assurance hardly possible by means of reliability aware design only. Thus, in order to achieve the Integrated Circuit (IC) lifetime reliability specification, a Dynamic Reliability Management (DRM) framework is required to predict the hardware resources ageing and to take the necessary actions, at circuit, architecture, and software levels in order to extend the system lifetime and/or prevent system failure. In this talk we present such an DRM framework able to perform architectural-level reliability assessment, prediction, and management based on reliability information provided by ageing sensors, which are monitoring the device/IC degradation caused by dynamic environmental stresses, e.g., NBTI and HCI.


Sorin D. COTOFANA received the M.Sc. degree in Computer Science from the "Politechnica" University of Bucharest, Romania, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He is currently an Associate Professor with the Electrical Engineering, Mathematics and Computer Science Faculty, Delft University of Technology, Delft, the Netherlands. His current research is focussed on: (i) the design and implementation of dependable/reliable systems out of unpredictable/unreliable components; (ii) ageing assessment/prediction and lifetime reliability aware resource management; and (iii) unconventional computation paradigms and computation with emerging nano-devices. He (co-)authored 37 journal, 177 international conference, and 38 local conferences and workshops papers. He received 12 international conferences best paper awards, e.g., 2012 IEEE Conference on Nanotechnology, 2012 ACM/IEEE International Symposium on Nanoscale Architectures, 2005 IEEE Conference on Nanotechnology, 2001 International Conference on Computer Design; He is currently Senior Editor for IEEE Transactions on Nanothechnology and Associate Editor for Nano Communication Networks journals, Steering Committee member for IEEE Transactions Transactions on Multi-Scale Computing Systems, and has been actively involved in the organisation of many international conferences. He is a HiPEAC member, a senior IEEE member (Circuits and System Society (CASS) and Computer Society), Chair of the GIga-Nano IEEE CASS Technical Committee, and IEEE Nano Council CASS representative.

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