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Prof. Sungjoo Yoo, POSTECH, Korea


Low Power Hybrid Memory Cube with Link On/Off Management


The Hybrid Memory Cube (HMC) is a 3D-stacked DRAM architecture designed for substantially improved memory bandwidth. In particular, its I/O interface achieves up to 320GB/s of external bandwidth through high-speed serial links. However, it comes at a cost of large static power of off-chip links, which dominates total power consumption of HMCs. Therefore, we propose an adaptive mechanism to partially disable off-chip links of HMCs with a minimal performance impact. We also present two-level prefetching with in-HMC prefetch buffers to further improve its efficiency in the presence of prefetching. Evaluations show that our scheme significantly reduces energy consumption of HMCs by 53% on average.


Sungjoo Yoo received Ph.D. from Seoul National University in 2000. He worked as researcher at TIMA laboratory, Grenoble France from 2000 to 2004. He was also principal engineer at Samsung System LSI from 2004 to 2008, where he led system-on-chip architecture design team and was involved in memory and bus architecture designs for mobile application processors and performance modeling and optimization of solid state disk. He joined POSTECH in 2008 and is now associate professor. His research interests include software and hardware design for low power SoC, and cache/memory and storage hierarchy based on emerging memory technologies such as phase-change RAM, spin-transfer torque RAM (including racetrack memory), resistive RAM and vertical NAND Flash memory. He received Best Paper Award at International SoC Conference (ISOCC) in 2006 and Best Paper Award nominations at Design Automation Conference (DAC) in 2011 and Design Automation and Test in Europe (DATE) in 2002 and 2009.

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