Slides available here!

Speaker:

Charlie Janac, Arteris, USA

Title:

Using SoC Interconnect IPs to Improve Physical Layout

Abstract:

Network on Chip(NoC) SoC interconnect IPs have improved SoC productivity and quality of results at the architectural level, now it is time for NoC interconnect to get "physical". The interconnect is the only IP that spans the entire chip and connects to vast majority of the IPs. Furthermore, the arrival of 16/14nm technologies, have made it important to manage physical design constraints at the architectural level and to use floorplan data, in combination with NoC interconnect IPs, to automate timing closure and provide improved data to place and route systems. The presentation will cover capabilities of Physical Aware interconnect to accelerate layout productivity and quality of results.

Bio:

K. Charles Janac is the Chairman, President and Chief Executive Officer of Arteris Inc.. Arteris has pioneered the market for use of Network on Chip (NoC) interconnect IP and Tools for on-chip communications in semiconductor chips. Arteris products are designed into some of the highest volume SoCs being delivered today by over 55 semiconductor companies.

Charlie has nearly 30 years of experience building technology companies. He started his technology career as employee number two of Cadence Design Systems (originally SDA Inc.), a publicly traded EDA software company. Subsequently, he served as President/CEO of HLD Systems, Smart Machines and Nanomix. Charlie also served as Entrepreneur-in-Residence at Infinity Capital, an early stage venture capital firm in Palo Alto, California.

Born in Prague, Czech Republic, he holds both a B.S. and M.S. degrees in Organic Chemistry from Tufts University and an MBA from Stanford Graduate School of Business. Charlie, his wife Lydia, reside in Los Altos Hills, California.



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