Slides available here!

Speaker:

Dr. Fumio Arakawa, Nagoya University, Japan

Title:

Nanoprocessor Cluster: Naturally Minimizing Active Portion for Dark-Silicon Era

Abstract:

Last year, I introduced Nanoprocessor Cluster to convert instruction level parallelism (ILP) to μ-thread level parallelism (μTLP) for the efficient parallelization of such a program with tightly-coupled long-latency operations. Each Nanoprocessor of the cluster naturally adjusts the execution timing without large buffers, which are used by conventional out-of-order processors, and make them large and consuming high power. Contrarily, a Nanoprocessor just transfers data without checking the receiving Nanoprocessor status, then the receiving one get the data on time or store the data to an overrun buffer, which can be slow. The overrun buffers are inactive during on time operations, and can be dark-silicon portion for most of the execution time by keeping on-time operations.

Bio:

Fumio Arakawa is a designated professor of Graduate School of Information Science at Nagoya University. His research interests include architecture and micro-architecture of low-power and high-performance microprocessors. Arakawa has a PhD in electrical engineering from the University of Tokyo. He's a program committee co-chair of the Cool Chips conference series, a program committee member of the VLSI Circuits Symposium, a steering committee member of International Symposium on Embedded Multi/Many-core SoCs, and the chairman of Microprocessor Technical Committee of Japan Electronics and Information Technology Industries Association. He's a member of IEEE and the Institute of Electronics, Information, and Communication Engineers.



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