Slides available here!

Speaker:

Tsuyoshi Isshiki, Tokyo Institute of Technology, Japan

Title:

C-Based RTL Design Framework for Hardware-IP and ASIP Synthesis

Abstract:

This talk introduces our recent work on a new C-based design framework for hardware-IPs and ASIPs (application-specific instruction-set processors). Unlike the traditional High-Level Synthesis flow, C descriptions are used to directly represent the RTL structures and behaviors, at the same time, serving as fast simulation models. First design case for our C-based framework is a complex image processing pipeline systems where 5000 lines of C codes is converted into highly parallel and pipelined RTL structure capable of performing more than 4000 operations per cycle. Second design case is a RISC processor where a cycle-accurate ISS (instruction-set simulator) is given as the C description that is directly translated into pipelined RTL description which contains caches and pin-accurate IO interfaces, all of which are fully described in C.

Bio:

Tsuyoshi Isshiki has received B.E. and M.E. degrees from Tokyo Institute of Technology in 1990 and 1992, respectively, and received PhD in Computer Engineering from University of California at Santa Cruz in 1996. He is currently a professor at Tokyo Institute of Technology, Global Scientific Information and Computing Center. His research interests include multimedia SoC designs, Multiprocessor SoC design methodology and its design tools.



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