Slides available here!

Speaker:

Mr. Yuichi Nakamura, NEC Corp., Japan

Title:

How to develop 4K realtime HEVC encoder by FPGA

Abstract:

Since 4K video system requires huge communication bandwidth, new high efficiency video codec system HEVC (High efficient video coding) is proposed. HEVC encoder can achieve high compression rate but its system architecture is very complicated. We completed to develop this complex and complicated HEVC encoder by only FPGA. In general, the system frequency of FPGA is relatively low and it is difficult to implement huge multiplexers. To overcome these disadvantages of FPGA implementation on HEVC encoder, we introduced 2 technologies, a parallel scheduling for transforming system and an intra prediction image generator method. According to these ideas, we can provide 4k/60p realtime HEVC encoder with broadcasting quality.

Bio:

Yuichi Nakamura received his B.E. degree in information engineering and M.E. degree in electrical engineering from the Tokyo Institute of Technology in 1986 and 1988, respectively. He received his PhD. from the Graduate School of Information, Production and Systems, Waseda University, in 2007. He is currently a general manager at Green platform Research Labs., NEC Corp. He is also a guest professor of National Institute of Informatics.



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