Abstract

Although ESL/HLS design technologies have evolved recently, system-level RTL verification is still the major bottleneck in today's complex SoC designs where critical design flaws may only be caught when the entire system is integrated and simulated at cycle-accuracy.

In this talk, we introduce our recent work on C-based system design framework (C2RTL) which is now ported to the LLVM compiler framework and greatly enhancing the design productivity with the use of C++ object-oriented RTL modeling methodologies. We take a simple SoC model with CPU/UART/SPI/TIMER connected via AXI interconnect as a design example and show how a complete SoC can be modeled, verified at cycle-accuracy, and RTL-synthesized from a single C++ description.

Biography

Tsuyoshi Isshiki has received B.E. and M.E. degrees from Tokyo Institute of Technology in 1990 and 1992, respectively, and received PhD in Computer Engineering from University of California at Santa Cruz in 1996. He is currently a professor at Tokyo Institute of Technology, Global Scientific Information and Computing Center. His research interests include multimedia SoC designs, Multiprocessor SoC design methodology and its design tools.