Lilia Zaourar

CEA LIST, France

Exploring the Multifaceted Design Space of Chipletization: Navigating Trends and Decision Making

Abstract

As the demand for compute-intensive applications including high-performance computing, embedded systems, mobile, and automotive increases, the semiconductor industry is pushing the boundaries of high transistor integration. To meet these ever-growing needs, Chiplet-based architecture has emerged as a solution for covering several product ranges, with minimal variants. Thus reducing costs, time to market, and faster creation of Integrated Circuits. Indeed, chiplets heterogeneous integration allows more freedom by adding many more dimensions to the design space inter and intra chiplets (partitioning, IP selection, interconnect) compared to monolithic SoC while escalating design complexity.

However, chipletization requires a new design paradigm that needs novel approaches at the architecture design level, particularly at the early stages of the architecture specification process.

To overcome this extra layer of complexity EDA tools are mandatory. Virtual prototypes allow analyzing the impact of preliminary architecture design decisions using various models while meeting application constraints. Automated exploration strategies are key elements to efficiently browse the design space and thus provide good choices to satisfy multiple and possibly conflicting design metrics.

This presentation will discuss early architecture decisions, considerations, trends, and challenges, and provide insights into methodologies and tools to achieve chiplet system-level architecture exploration for chiplets’ success.

Biography

Dr. Lilia Zaourar is a CEA expert in co-design techniques for Computing Architectures at CEA LIST.  She received an MS and PhD in Operational Research and Computer Science from the University Joseph Fourier, Grenoble, in 2007 and 2010, respectively. She developed various optimization algorithms for the design and test of integrated circuits. Then, she was a temporary teaching and research assistant at the SoC department in Computer Science PARIS 6 Laboratory, Sorbonne University, from 2010 to 2012. She was involved in developing optimization strategies for the resource-sharing problem to test embedded memories. She joined the CEA LIST in 2012 and has participated in various national, European, and industrial research projects on real-time mixed-criticality systems, optimization strategies of runtime software for heterogeneous HPC and microservers, and FPGA emulation.

She led Modelling and Simulation activities within the first phase of the European Processor Initiative (EPI) project. She is currently involved in the second phase of EPI on co-design and exploration. Her research interests cover combinatorial optimization and operational research techniques with a special focus on optimization problems for electronic design automation and high-performance embedded systems, as well as testing and security. She is the project leader of the working group ” ” funded by the French institution CNRS. She has been a SAMOS, SC, PMBS, and CoDit technical programs member. She has served as General Chair for Hipeac/Rapido 2023, 2024, and General Chair of the 50th Euromicro DSD/SEAA 2024 conference.