Yiran Chen

Duke University, USA

Low-Power Superconducting Qubit Readout Using Single-Flux-Quantum Circuits

Abstract

Realizing large-scale superconducting quantum computers requires extremely low-power peripheral circuits that can operate within the limited cooling capacity of dilution refrigerators,. In particular, the heat generated by readout and control interfaces at the 4 K stage poses a significant challenge to system scalability,.
This presentation introduces a low-power and reliable peripheral circuit for Josephson Photomultiplier (JPM)-based qubit readout utilizing a Single-Flux-Quantum (SFQ) counter circuit. Our approach employs a multi-shot readout scheme where the counter performs majority voting near the readout circuit at the 4 K stage. To achieve significant power savings, we deliberately reduce the critical current Ic of the Josephson junctions to lower the switching energy. While low-Ic junctions are more susceptible to thermal noise and switching errors, the proposed majority voting logic effectively mitigates these impacts.
Through JoSIM SPICE-level simulations and stochastic state transition analysis, we demonstrate that the proposed scheme can reduce power consumption at the 4 K stage by approximately 90% compared to conventional single-shot readout while maintaining high reliability. This technology contributes to the development of a scalable quantum-classical interface necessary for future fault-tolerant quantum computing.

Biography

He received his Ph.D. from Kyushu University, Japan, in 2009. In 2010, he joined Fujitsu Laboratories Ltd., Kawasaki, Japan, as a researcher. From 2015 to 2026, he served as an assistant professor and subsequently as an associate professor at Kyushu University. He is currently a professor in the Department of Electronics Engineering and Computer Science at Fukuoka University, Japan.
His research interests lie broadly in computer architecture, with particular emphasis on superconducting computing, nanophotonic computing, memory systems (including non-volatile memory), secure computing, and high-performance computing. He is a member of the IEEE, the Information Processing Society of Japan (IPSJ), and the Institute of Electronics, Information and Communication Engineers (IEICE).