The University of Tokyo, Japan
Architecture extension and implementation analysis of physical memory protection of RISC-V
Trusted Execution Environment Task Group (TEE TG) of RISC-V extended the architecture of physical memory protection (PMP). As a member of the TG, we will introduce the extension, which provides memory isolation feature between machine and other modes and flexibility of the PMP setting. The PMP provides very flexible protection setting, but requires considerable amount of hardware especially for low-end processor cores. So, we analyzed the area overhead of the PMP implementation, and will present the results.
Fumio Arakawa is a designated researcher of d.lab at the University of Tokyo, and a designated professor of Graduate School of Informatics at Nagoya University. His research interests include architecture and micro-architecture of low-power and high-performance processors. He has founded an R&D and consulting company, Famer Systems, Inc. to contribute on industries with his R&D experience of Hitachi and Renesas Electronics. He is a program committee co-chair of the Cool Chips conference series, and the chairman of Microprocessor Technical Committee of JEITA. He served as a Guest Editor of IEEE Micro for six times, and TPC members of conferences including ISSCC, VLSI Circuits Symposium, A-SSCC, and MCSoC. He has a Ph.D. in electrical engineering from the University of Tokyo. He is a member of IEEE and IEICE.
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