The University of Tokyo, Japan
Introduction of AI-Chip Design Center and Evaluation of RISC-V
In Japan, there are many seeds that can create new businesses based on AI chips, mainly in venture companies. However, AI chip design requires expensive EDA tools, IPs, and verification devices such as an emulator, which are high hurdles for commercializing the seeds. So, we are developing the design and verification environment necessary for AI chip design, and will accelerate the R&D of AI chips to realize innovations. AI-One chip that integrates multiple AI accelerators is the first outcome of the AI-Chip Design Center, and achieved 45% or less period of design and evaluation. Further I’ll show two evaluation results of RISC-V, which are “Linux boot with RISC-V processor on Cadence emulator” and “Applicability of RISC-V security specifications to low-end processors”.
Fumio Arakawa is a designated researcher of d.lab at the University of Tokyo, and an invited professor of Graduate School of Informatics at Nagoya University. His research interests include architecture and micro-architecture of low-power and high-performance processors. He has founded an R&D and consulting company, Famer Systems, Inc. to contribute on industries with his R&D experience of Hitachi and Renesas Electronics. He is an organizing committee co-chair of the Cool Chips conference series, and the chairman of Microprocessor Technical Committee of JEITA. He served as a Guest Editor of IEEE Micro for seven times, and TPC members of conferences including ISSCC, VLSI Circuits Symposium, A-SSCC, and MCSoC. He has a Ph.D. in electrical engineering from the University of Tokyo. He is a member of IEEE and IEICE.
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