Lana Josipovic

ETH Zurich, Switzerland

Estimating Circuit Quality Directly from HLS Source Code

Abstract

High-Level Synthesis (HLS) compilers enable programmers to automatically generate hardware designs from high-level software abstractions instead of writing tedious and time-consuming low-level hardware descriptions. However, today’s HLS compilers are still accessible only to expert users and for particular classes of applications; generating good-quality circuits still requires peculiar code restructuring and extensive experimentation with the tools. In this talk, I will discuss the challenges and limitations of current HLS approaches. I will describe Balor, our fast and accurate circuit quality estimator that enables efficient HLS design space exploration. Finally, I will share my vision on future advancements of HLS and hardware design.

Biography

Lana Josipović is an Assistant Professor in the Department of Information Technology and Electrical Engineering at ETH Zurich. Prior to joining ETH Zurich in 2022, she received a Ph.D. in Computer Science from EPFL. Her research interests include reconfigurable computing and electronic design automation. She is a recipient of various research awards, including the EDAA Outstanding Dissertation Award, EPFL Doctorate Award, Google Ph.D. Fellowship in Systems and Networking, and Best Paper Awards at ISFPGA’20 and FPL’24. She is an Associate Editor for IEEE TCAD, ACM TRETS, and ACM TODAES, and served as general, program, and topic chair of several international conferences and workshops, including IWLS, FCCM, FPL, DAC, and DATE.