Partha Pande
Washington State University
Evolution of Manycores to Many Chiplets: A journey of two decades
Abstract
The Chips and Science Act opened new opportunities in microelectronics research and workforce generation. A multitude of governmental and industrial efforts in semiconductor research are initiated, providing unprecedented opportunities for academic research, university/industry partnerships, and educational initiatives. With almost two decades of experience in manycore heterogeneous architectures and 3D chip design in my group, we are in an advantageous position to tackle the challenges associated with technology scaling and heterogeneous integration. Heterogeneous integration (HI) for the next generation of semiconductor systems has emerged as the enabler of continued progress to achieve high performance and energy efficiency, as monolithic chips have become prohibitive due to manufacturing cost and fabrication challenges. Hence, with its potential impact on a wide range of applications, from high-performance computing to biotechnology, HI plays an important role in the modern-day economy and is crucial for national security.
In this talk, I will first provide an overview of our research on various aspects of heterogeneous manycore computing platforms enabled by the Network-On-Chip (NoC) paradigm that represents a powerful alternative to the data center-oriented type of computing. Next, I will emphasize on the interplay between machine learning and manycore systems. I will elaborate on how our work enables a virtuous cycle of ML techniques for advancing hardware designs spanning from edge devices to the cloud, which will empower further advances in ML (a.k.a. ML for ML). Following this, I will present our recent work on the emerging 2.5D chiplet platforms that provide a new avenue for compact scale-out implementations of various data- and compute-intensive workloads. Integrating multiple small chiplets using a Network-on-Interposer (NoI) offers not only significant cost reduction and higher manufacturing yield than 2D ICs but also better energy efficiency and performance. I will conclude this presentation by highlighting the future roadmap of ML-enabled heterogeneous architectures with different types of sensors, memory, and processing chiplets enabled by advanced packaging.
Biography
Partha Pratim Pande is the Dean of the Voiland College of Engineering and Architecture (VCEA) at Washington State University, Pullman, and the Boeing Centennial Chair Professor in Computer Engineering in the School of Electrical Engineering and Computer Science. Dr. Pande’s research has fundamentally advanced the design of scalable manycore systems, pioneering innovations in interconnect architectures, on-chip wireless communication networks, heterogeneous computing, and the application of machine learning to electronic design automation (EDA). His work has significantly influenced the evolution of next-generation computing platforms, addressing critical challenges in performance, scalability, and energy efficiency. Dr. Pande currently serves as Editor-in-Chief of IEEE Design & Test, one of the field’s flagship publications, and he is also the Editor-in-Chief of the ACM Journal on Emerging Technologies in Computing Systems (JETC). His leadership has helped shape research directions at the intersection of computing architecture and emerging technologies. He has also played key roles in premier international conferences, including serving as Technical Program Chair of the IEEE/ACM International Symposium on Networks-on-Chip and CASES, and contributing extensively to technical program committees of leading venues worldwide. His contributions have been recognized through numerous prestigious honors, including the NSF CAREER Award, the Anjan Bose Outstanding Researcher Award from Washington State University, nine best paper awards and multiple additional best paper award nominations. Dr. Pande is a Fellow of IEEE and a Distinguished Member of ACM.
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