Frederic Rousseau

Grenoble-Alpes University, France

HW Cache Evolution to Support Sparce Matrix Vector Multiplications

Abstract

Improvements in computer performance depend increasingly on specialized accelerators and recently, numerous architectures optimized for sparse matrix kernels have been proposed, however, they do not exploit the structural properties of the matrices.

SpDCache is a cache for outer-product Sparse Matrix-Vector Multiplication (SpMV) which has storage strategies optimized for both dense and sparse regions and which performs reductions locally in this cache. Real world matrices typically have a dense band which benefits from being blocked in the dense region of our cache, while the sparse regions benefit from fine-grained storage and a shift of the computation close to the main memory. We present the architectural principals of SpDCache and show that it reduces main memory traffic by ∼ 8× and increases the cache utilization by ∼ 2× for banded matrice.

Biography

Pr Frédéric Rousseau received the Engineer degree in computer science and electrical engineering from the University of Grenoble in 1991 and a Ph.D. in computer science in 1997 from the University of Evry – France. He has hold an assistant professor position at the University of Grenoble since October 1999 and a professor position since 2007. He is researcher in TIMA lab. His research interest concerns Multi-Processor Systems-on-Chip design and architecture, prototyping of hardware/software systems, including reconfigurable systems and high-level synthesis for embedded systems.

Download