Takahide Yoshikawa

Fujitsu Ltd., Japan

Acceleration of Nonlinear Operations in AI by Reconfigurable Architecture: Exploring the Flexibility–Performance Trade-off

Abstract

As demand for AI continues to grow rapidly, performance scaling through conventional approaches is reaching its limits, making algorithmic and architectural innovations increasingly critical. AI workloads can be broadly decomposed into three components: matrix operations, communication, and nonlinear operations. While our presentation last year introduced the Fugaku LLM project, which highlighted acceleration techniques for matrix computation and communication, this talk focuses on the often-overlooked nonlinear components, such as normalization and activation functions. We explore the potential of reconfigurable architectures—ranging from fine-grained FPGAs to coarse-grained CGRAs—to accelerate these operations. In particular, we discuss the fundamental trade-off between flexibility and performance as architectural granularity changes and examine how to navigate it to design efficient AI processing systems. This work provides new insights into expanding the design space of next-generation AI accelerators.

Biography

Takahide Yoshikawa is a Director and Head of the Advanced Computing R&D Centre, Fujitsu Canada. He received his B.E., M.E., and Ph.D. degrees from the University of Tokyo in 1994, 1996, and 2002, respectively, and he is a Senior Member of IEEE. He has been involved in various server system projects, including the K computer and Fugaku. In the K computer project, he proposed and implemented the entire verification, validation, and testing system for its interconnect, Tofu. In Fugaku, he led the verification and validation of the CPU. Currently, he is tackling research on the architecture of the future high-performance AI accelerator system.

Anh Nguyen is a Principal Researcher at Fujitsu Research, where she advances design methodologies for next‑generation computing systems. She received her M.S. and Ph.D. degrees in Information and Communication Engineering from the Tokyo Institute of Technology, Japan, in 2018 and 2021, respectively. Her research spans reconfigurable architectures, computer‑aided design (CAD) methodologies, high‑level hardware design, and hardware/software co‑optimization. Her work aims to enable efficient, scalable, and adaptive hardware platforms capable of meeting the demands of emerging computing workloads.