Abstract

For efficient execution of embedded to high performance applications on multicore processors, optimal use of cache memory or local memory of each processor core is very important. Especially, in hard real time control systems, the optimal use of local memory to keep deadlines is essential. This talk introduces automatic cache and local memory management methods called “data localization” implemented on OSCAR parallelizing and power reducing compiler. The data localization method decomposes the data dependent loops and their data so that their working sets accessed by the data dependent decomposed loops can fit to the cache or local memory of each core. At that time, if one dimensional data and loop decomposition are not sufficient to load the working set to each cache or local memory, the data and loops are decomposed multi-dimensionally. Next, the decomposed working sets are assigned to each core so that the decomposed data assigned onto the processors can be reused over data dependent loops as much as possible. At that time, when the local memory is used, the data transfers using Data Transfer Units, or smart DMA controllers, are optimized. The performance of the memory optimization method implemented on the OSCAR compiler is evaluated using various embedded and scientific application programs.

Biography

Hironori Kasahara is IEEE Computer Society (CS) 2018 President and 2017 President Elect and has served as a chair or member of 245 society and government committees, including the CS Board of Governors; Executive Committee; Planning Committee; chair of CS Multicore STC and CS Japan chapter; associate editor of IEEE Transactions on Computers; vice PC chair of the 1996 ENIAC 50th Anniversary International Conference on Supercomputing; general chair of LCPC; PC member of SC, PACT, and ASPLOS; board member of IEEE Tokyo section; and member of the Earth Simulator committee.

He received a PhD in 1985 from Waseda University, Tokyo, joined its faculty in 1986, and has been a professor of computer science since 1997 and a director of the Advanced Multicore Research Institute since 2004. He was a visiting scholar at University of California, Berkeley, and the University of Illinois at Urbana–Champaign’s Center for Supercomputing R&D.

Kasahara received the CS Golden Core Member Award, IEEE Fellow, IFAC World Congress Young Author Prize, IPSJ Fellow and Sakai Special Research Award, and the Japanese Minister’s Science and Technology Prize. He led Japanese national projects on parallelizing compilers and embedded multicores, and has presented 214 papers, 139 invited talks, and 28 patents. His research on multicore architectures and software has appeared in 560 newspaper and Web articles.