17th INTERNATIONAL FORUM ON MPSoC
for software-defined hardware
Speaker's Profile
Abstract
The ongoing research on Neural Networks includes work to reduce the computation and storage requirements for these networks. One of the promising opportunities is the reduction of the compute and storage down to a full binarization. In this talk, we will show a framework for implementing Neural Networks, including these Reduced Precision and Binarized Neural Networks, leveraging C/C++ implementations with High Level Synthesis. Recent research has shown that the accuracy of reduced precision networks is approaching the accuracy of similar networks with Floating Point, 16-bit or 8-bit operations. The results on accuracy exploiting re-training will be presented. The architecture and detailed implementation of the latest large networks will be presented. It will be shown that Tera-ops of performance can be achieved in modern FPGAs with limited power consumption.
Biography
Kees Vissers graduated from Delft University in the Netherlands. He worked at Philips Research in Eindhoven, the Netherlands, for many years. The work included Digital Video system design, HW –SW co-design, VLIW processor design and dedicated video processors. He was a visiting industrial fellow at Carnegie Mellon University, where he worked on early High Level Synthesis tools. He was a visiting industrial fellow at UC Berkeley where he worked on several models of computation and dataflow computing. He was a director of architecture at Trimedia, and CTO at Chameleon Systems. He is recognized contributor to the Chapter on VLIW processors in the book: Computer Architecture, 5th edition: A quantitative approach by John L. Hennessy and David A. Patterson He was a Board member of Beecube, which is now part of National Instruments. Today he is heading a team of researchers at Xilinx, including a significant part of the Xilinx European Laboratories. The research topics include next generation programming environments for processors and FPGA fabric, high-performance video systems, wireless applications and new datacenter applications. He has been instrumental in the architecture of Zynq and MPSoC and the novel programming environments, leveraging High-Level Synthesis technology. He is continuously driving new architectures and programming environments. His current research includes work on Neural Networks and reduced precision Neural Networks.