Keiji Kimura

Waseda University, Japan

Vector Multicore and Cascaded DMAC Accelerating Indirect Memory Access Applications

Abstract

Indirect memory accesses caused by sparse linear algebra calculations are widely used in important real applications. However, they also cause serious inefficient memory accesses and pipeline stalls resulting in low execution efficiency even with high memory bandwidth and much computational resource. To overcome this situation, we proposed a Cascaded-DMAC (CDMAC). This CDMAC is intended to be attached in each core of a vector multicore chip. It performs data transfers between an off-chip main memory and an in-core local data memory, which provides data to the vector accelerator in a core.

The key idea of the CDMAC is cascading two DMACs for indirect memory accesses so that the first one loads indices, then the second one accesses data elements by using these indices. Thus, this organization realizes the efficient SIMD computations by lining up the sparse data into the local data memory. We implemented a vector multicore processor having the proposed CDMAC on an FPGA board. The evaluation result of sparse matrix-vector multiplications on the FPGA shows that the CDMAC achieves 14x speedup at most compared with the CPU data transfer.

Biography

Keiji Kimura received the Ph. D degrees in electrical engineering from Waseda University in 2001. He was an assistant professor in 2004, associate professor in 2005, and professor in 2012 at Waseda University. He is a director of Green Computing System Research Organization in Waseda from 2019. He is a recipient of 2014 MEXT (Ministry of Education, Culture, Sports, Science and Technology in Japan) award. His research interest includes multicore processor architecture and parallelizing compiler technologies. He is a member of IPSJ, ACM and IEEE. He has served on program committee of many conferences.