SESSION 2: Memory/Cache/Storage
(IN-Depth Technical Presentation and Mini-Keynote)

SESSION 3: High Performance Computing
(In-Depth Technical Presentation)

SESSION 4: Continuing MOORE's Law
(In-Depth Technical Presentation)

SESSION 5: Keynote

SESSION 8: Software
(In-Depth Technical Presentation and Mini-Keynote)

SESSION 9: Keynote

SESSION 11: Multicore Architecture
(Mini-Keynote)

SESSION 12: Keynote

SESSION 14: Architecture
(In-Depth Technical Presentation)

Kerry Bernstein
Kerry Bernstein is a Research Staff Member at the IBM T.J. Watson Research Center. Mr. Bernstein received the B.S degree in electrical engineering degree from Washington University in St.Louis in 1978, and has been with IBM for 32 years. He holds 105 US Patents, and is a co-author of 3 college textbooks and multiple papers on high speed / low power CMOS. His research interests are in the areas of emerging device / circuit architectures for future high performance computing; 3D integration; radiation effects in CMOS; and Silicon-on-Insulator (SOI) transistors. Mr. Bernstein is an IEEE Fellow.

Sungjoo Yoo
Sungjoo Yoo is currently an assistant professor at Department of EE, POSTECH, Korea. He received Ph.D. from Seoul National Univ. in 2000. He worked as researcher at TIMA laboratory, Grenoble France from 2000 to 2004. He was also with Samsung System LSI from 2004 to 2008, where he led system-on-chip architecture design team and was involved in architecture designs for mobile application processors and solid state disk. He joined POSTECH in 2008. His research interests include memory and storage hierarchy from cache, DRAM, phase-change RAM to solid state disk. He received Best Paper Award at International SoC Conference (ISOCC) in 2006 and Best Paper nominations at Design Automation Conference (DAC) in 2011 and Design Automation and Test in Europe (DATE) in 2002 and 2009.

Hsien-Hsin Sean Lee
Dr. Hsien-Hsin S. Lee is an Associate Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology. He has a Ph.D. degree in Computer Science and Engineering from the University of Michigan, Ann Arbor. His current research interests include computer architecture, memory hierarchy, low-power VLSI, cyber security, and 3D-IC technology. Prior to joining Georgia Tech in 2002, he spent 6 years as a senior processor architect and a research staff member at Intel Corporation designing Pentium III processor and conducted research for Itanium architecture and one year at Agere Systems as an architecture manager for their StarCore DSP architecture. Dr. Lee’s received the Horace H. Rackham Distinguished Dissertation Award from the University of Michigan, an NSF CAREER Award, a Department of Energy Early CAREER Award, and the Georgia Tech ECE Outstanding Jr. Faculty Award. He had co-authored 3 papers that won Best Paper Awards, one paper selected in 2010 IEEE MICRO Top Picks, and holds 4 U.S. patents. He is a senior member of both the ACM and the IEEE.

Hiroyuki Tomiyama
Hiroyuki Tomiyama received his Ph.D. degree in computer science from Kyushu University in 1999. From 1999 to 2001, he was a visiting postdoctoral researcher with the Center of Embedded Computer Systems, University of California, Irvine. Then, he worked for Institute of Systems & Information Technologies/KYUSHU as a researcher and Nagoya University as an associate professor. In 2010, he moved to Ritsumeikan University as a full professor. His research interests include system-level design methodology for embedded systems and MPSoC. He was General Co-Chair of MPSoC 2010, and is now Editor-in-Chief of IPSJ Transactions on System LSI Design Methodology.

David Kleidermacher
David Kleidermacher is Chief Technology Officer at Green Hills Software where he is responsible for technology strategy, platform planning, and solutions design.  Kleidermacher is a leading authority in systems software and security, including secure operating systems, virtualization technology, and the application of high robustness security engineering principles to solve computing infrastructure problems. Kleidermacher earned his bachelor of science in computer science from Cornell University and has been with Green Hills Software since 1991

Raphaël David

Soo-Ik Chae
Ph. D. Electrical Engineering from Stanford University, Stanford, California, in 1987
“Defect Detection and Classification for VLSI Pattern Inspection”
M. S. Electrical engineering from Seoul National University, Seoul, Korea, in 1978
B. S. Electrical engineering from Seoul National University, Seoul, Korea, in 1976

Dongrui Fan
Dongrui Fan received Ph.D. degree of computer architecture in 2005 from Institute of Computing Technology, Chinese Academy of Sciences, and now he is an Associate Professor of the institute since 2006. Dongrui participated Godson-1 and Godson-2 micro-architecture designs from 2000. Currently, his research interests focus on multi-core/many-core architecture and low-power embedded micro-architecture design. He leads AMS research group and designed the new processor models -- Godson-X and Godson-T, which are research on the new generation Godson series chips. Dongrui is Technical Committee Member of Computer Architecture and System Software of China Computer Federation (CCF) and HiPEAC/IEEE/ACM member. He serves as a Program Committee Member of the International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT) in 2009 and 2010. He also serves as the Program Vice-Chair of Multi-Core and Parallel Systems in the International Conference on Parallel Processing (ICPP) in 2011, and several workshops. Dongrui leads or participates many Chinese national science projects and EU FP7 project. He published papers on MICRO, IPDPS, CF, EuroPar, Trans. on HiPEAC, etc.

Paolo Faraboschi
Paolo is a Distinguished Technologist in the Intelligent Infrastructure Lab of HP Labs. From 2004 to 2010, Paolo led a research group in Barcelona (Spain) focused on system-level simulation and modeling of next-generation computing systems (the COTSon simulator was released as open source in 2010). From 1995 to 2003 Paolo was the technical lead of the Custom-Fit Processors Project at HP Labs in Cambridge (MA). In that role, he was the principal architect of the the Lx/ST200 family of VLIW embedded processor cores (in partnership with STMicro), which as of 2009, shipped in over 70 million embedded devices. Paolo holds a Ph.D (Dottorato) in EECS (1993) and an M.S. (Laurea) in Electrical Engineering (1989) from the University of Genoa (Italy). He is an active member of the computer architecture community, and regularly serves in program and organization committees. He was Program Chair for HiPEAC'10, MICRO'41, MICRO'34, CASES'03; General Chair for MICRO'38 and CASES'05. He is a co-author of the book "Embedded Computing: a VLIW approach to architecture, compilers and tools", serves in the industrial advisory board of the HiPEAC European network of excellence, and is currently an Associated Editor of ACM TACO.

Patrick Blouet
Patrick Blouet is an electronic and computer science engineer. He holds a Master degree from ENSERB in 1981 in France. He started working in a large telecommunication company where he designed a number of medium size systems in the domain of private PABX. Then he moved in a startup doing system engineering. He developed numerous systems in the domain of hard real time, telecommunications, large multi-processing, image processing and storage. During this period, he used to run large projects with multiple partners. He then took the position of BU manager for all the imaging products in charge of marketing and technical strategy. He joined STMicroelectronics where he took the responsibility of development tools and applications for DSP’s. He developed the activities and was heavily involved in the creation of a large DSP R&D centre in Singapore. In addition, he took the marketing responsibility of DSP products for telecom applications. He then moved in the application processor division where he held the Architecture director position in charge of defining all the mobile products. He then moved to the Corporate partnerships and public affairs team at ST-Ericsson where is in charge of building and running collaborative projects at European, national and regional level.

John Goodacre


Michael Chang
VP of Engineering
Global Unichip Corp.
Mr. Chang possesses over twenty five years of designing ASIC and SoC experience, and has served many key R&D positions.  .
Prior joining GUC, Mr. Chang has served as Sr. Director of ASIC Design in ESS, VP of VLSI design in Divio, and VP of R&D in Prolific

Bing Sheu
Bing SHEU obtained B.S. degree in EE from National Taiwan University, and his Ph.D. degree in EE from University of California, Berkeley. He joined EE faculty at University of Southern California (Los Angeles, CA) during 1985 – 1998, and was promoted to Full Professor in 1997 in Electrical Engineering with adjunct appointment in Biomedical Engineering. He moved to microelectronics and design automation industry in early 1999 and joined TSMC in 2006 as Director at R&D Design and Technology Platform. He served as Editor-in-Chief of IEEE Transactions on VLSI Systems in 1997 & 98, as Founding Editor-in-Chief of IEEE Transactions on Multimedia in 1998 & 99, as Society Vice President for Conferences in 1998, as President of IEEE Circuits and Systems Society in 2000, and on Editorial Board of Proceedings of the IEEE during 2005 – 2010. Dr. Sheu is recipient or co-recipient of IEEE Transactions on VLSI Systems Best Paper Award in 1995, IEEE Guillemin-Cauer Award in 1997, IEEE CAS Society Golden Jubilee Award in 2000, IEEE CAS Society Meritorious Service Award in May 2004, and Education Contribution Award from Ministry of Education (Taiwan) in 2006. Dr. Bing Sheu is a 1996 IEEE Fellow, and 1998 Senior Fulbright Scholar from US Information Agency. He is granted Honorary Chair Professor from National Chiao Tung University in 2003 and Honorary Chair Professor from National Taiwan University of Science and Technology in 2011.

Koji Inoue
Koji Inoue was born in Fukuoka, Japan in 1971. He received the B.E. and M.E. degrees in computer science from Kyushu Institute of Technology, Japan in 1994 and 1996, respectively. He received the Ph.D. degree in Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University, Japan in 2001. He is currently an associate professor of the Department of Advanced Information Technology, Kyushu University. His research interests low-power cache architectures, power-aware computing, high-performance computing, and secure computing.

Yukoh Matsumoto
Dr. Yukoh Matsumoto is the chief architect, and president and CEO of TOPS Systems Corp. Currently, he leads “3-D stacked heterogeneous Multi-Processor chip project” funded by NEDO, as well as “Ultra-Android project”, embedded software platform to utilize heterogeneous Multi-Core processors, funded by METI. In his 25 years of carrier, he has architected and designed over 10 advanced Multi-Core processors, x86 microprocessors, and DSPs. He funded TOPS Systems Corp. in 1999, and received the Takeda Techno-Entrepreneurship Award in 2001. Prior to it he has held several positions within Texas Instruments Research and Development organization and within V.M. Technology, a microprocessor start-up in Japan. He received the Dr. of Information Sciences (the Ph.D.) degree from the Graduate School of Tohoku University, Sendai, Japan, in 2007 and participated in the MOT (Management of Technology) program at the Graduate School of Engineering in Tokyo University from 2004 through 2005.

David Atienza
David Atienza received his MSc and PhD degrees in Computer Science and Engineering from Complutense University of Madrid (UCM), Spain, and Inter-University Micro-Electronics Center (IMEC), Belgium, in 2001 and 2005, respectively. Currently, he is Professor and Director of the Embedded Systems Laboratory (ESL) at EPFL, Switzerland, and Adjunct Professor at the Computer Architecture and Automation Department of UCM. His research interests focus on design methodologies for low-power embedded systems and high performance Systems-on-Chip (SoC), including new thermal management techniques for 2D and 3D Multi-Processor SoCs, design methods and architectures for wireless body sensor networks, dynamic memory management and memory hierarchy optimizations, as well as novel architectures for logic and Network-on-Chip (NoC) interconnects. In these fields, he is co-author of more than 150 publications in prestigious journals and international conferences. He has received a Best Paper Award at the IEEE/IFIP VLSI-SoC 2009 Conference, two Best Paper Award Nominations at the ICCAD 2006 and DAC 2004 conferences. He is an Associate Editor of IEEE Transactions on CAD (in the area of System-Level Design), IEEE Letters on Embedded Systems and Elsevier Integration: The VLSI Journal. He is also an elected member of the Executive Committee of the IEEE Council of Electronic Design Automation (CEDA) since 2008 and a GOLD member of the Board of Governors of IEEE Circuits and Systems Society (CASS) since 2010.

Yuan Xie
Yuan Xie received the B.S. degree in electronic engineering from Tsinghua University, Beijing, in 1997, and the M.S. and Ph.D. degrees in electrical engineering from Princeton University in 1999 and 2002, respectively. He is currently Associate Professor in Computer Science and Engineering department at the Pennsylvania State University. Before joining Penn State in Fall 2003, he was with IBM Microelectronic Division's Worldwide Design Center. Prof. Xie is a recipient of the National Science Foundation Early Faculty (CAREER) award, the SRC Inventor Recognition Award, IBM Faculty Award, and several Best Paper Award and Best Paper Award Nominations at IEEE/ACM conferences. He has published more than 100 research papers in journals and refereed conference proceedings, in the area of EDA, computer architecture, VLSI circuit designs, and embedded systems. His current research projects include: three-dimensional integrated circuits (3D ICs) design, EDA, and architecture; emerging memory technologies; low power and thermal-aware design; reliable circuits and architectures; and embedded system synthesis. He is currently Associate Editor for ACM Journal of Emerging Technologies in Computing Systems (JETC), IEEE Transactions on Very Large Scale Integration Systems (TVLSI), IEEE Transactions on Computer Aided Design of Integrated Circuits (TCAD), IEEE Design and Test of Computers, IET Computers and Digital Techniques (IET CDT).

Ahmed Jerraya


Tohru Ishihara
Tohru Ishihara received the B.E., M.E., and D.E. degrees in  computer science from Kyushu University, Fukuoka, Japan, in 1995, 1997,  and 2000, respectively. From 1997 to 2000, he was a Research Fellow of the Japan Society for the Promotion of Science. For the next three  years, he was a Research Associate in the VLSI Design and Education  Center, University of Tokyo. From 2003 to 2005, he was with Fujitsu  Laboratories of America as a Research Staff of an Advanced CAD  Technology Group. From 2005 to 2011, he was with Kyushu University as an  Associate Professor. In April 2011 he joined Kyoto University, where he  is currently with the Dept. of Communications and Computer Engineering.  His research interests include low-power design methodologies and power  management techniques for embedded systems. Dr. Ishihara is a member of  the IEEE, ACM, IPSJ and IEICE. He was an executive committee member of  the DATE conference from 2009 to present and an OC member of the ASP-DAC  2001, 2008, 2009 and 2011. He was in the TPC of the DATE 2007, 2008, and  2009, the ISQED 2008 and 2009, and the ISLPED from 2009 to present.

Yoshinori Takeuchi
Yoshinori Takeuchi is Associate Professor of Graduate School of Information Science and Technology at Osaka University. He received his B.E., M.E. and Dr. Eng. degrees from Tokyo Institute of Technology in 1987, 1989 and 1992, respectively. From 1996, he has been with the Osaka University. He was a visiting scholar in University of California, Irvine from 2006 to 2007. His research interests include System Level Design, VLSI design and VLSI CAD. He is a member of  ACM, and Computer, CAS, SSC, and SP Society of IEEE.

Edith Beigne
Edith BEIGNE received a M.S. in microelectronics engineering from the National Polytechnic Institute of Grenoble in 1998. She joined in 1998  CEA-Leti working on asynchronous NoC and mixed-signal circuits focusing on high energy efficiency systems. She is now in charge of low power and variability research activities in advanced CMOS technologies specifically focusing on dynamically adaptive MPSoC architectures.

Youn-Long Lin
Dr. Youn-Long Lin is a professor with the Department of Computer Science, National Tsing Hua University, Taiwan. His research interest includes: high-level synthesis, video coding architecture design, and SOC design methodology. He received B.S. from National Taiwan Institute of Technology in 1982 and Ph.D. from the University of Illinois at Urbana-Champaign in 1987. He is a co-founder of Global UniChip Corp.

Yuichi Nakamura


Emil Matus
Dr. Emil Matus is senior scientist at Vodafone Chair Mobile Communication Systems where he is leading HW research group. He received his MS and PhD degrees in Electrical Engineering from University of Technology in Kosice. Prior to joining Vodafone chair in 2003 he was research associate at University of Technology in Kosice focused on wavelet transform and image compression. His current research interests include algorithms and many-core programmable architectures for communication signal processing.

Jenq-Kuen Lee
Jenq Kuen Lee received the B.S. degree in computer science from National Taiwan University in 1984. He received a Ph.D. in computer science from Indiana University in 1992, where he also received a M.S. (1991) in computer science. He was a key member of the team who developed the first version of the pC++ language and SIGMA system while at Indiana University. He was also a recipient of the most original paper award in ICPP '97 with the paper entitled "Data Distribution Analysis and Optimization for Pointer-Based Distributed Programs". In 2005, he received Taiwan MOEA funding to lead a research team to develop compilers for PAC VLIW DSP processors with distributed register files by collaborating with ITRI STC. The efforts were renewed in 2008 for another three years focusing on embedded multi-core compilers and applications. He is also a recipient of Google Research Award (Mountain View), 2009. He has also been a director for Taiwan MOE ESW (embedded system software) consortium since 2008. In 2010, he received a Taiwan MOEA economic contribution award (Deep Plow Award) for his contribution in embedded compiler research. His research interests are in optimizing compilers, embedded compilers, and computer architectures.

Alain Artieri
Alain Artieri  is a Senior Fellow at ST-Ericsson, a 50/50 joint venture by STMicroelectronics and Ericsson, where he is responsible for the technology roadmap for application processors. Prior to taking on this role, he was a Senior Director at Qualcomm, in charge of the Multimedia & Graphics cores development.  Before this assignment, he worked for more than 2 decades for STMicrolectronics where he  founded the Set Top Box SoC product family in the early 90’s  and Nomadik application processor product family in 2001.  During his  26 years experience in the Semiconductor industry, he has developed advanced ICs and SoCs  accross 12 CMOS generation with key contributions to multimedia architecture, power management architecture, low power design solutions and SoC architecture. He is now embarked on the exciting role of defining the right technologies for  Mobile Computing. Alain Artieri graduated from “ENST Paris” in 1984.

Ruchir Puri
Ruchir Puri received M.Tech. degree in electrical engineering from Indian Institute of Technology (IIT), Kanpur, India in 1990, and a Ph.D. degree in electrical and computer engineering from University of Calgary, Alberta, Canada in 1994. From 1994 to 1995 he was a Member of Scientific Staff with Advanced System Design Tools group at NORTEL Research (BNR). He joined VLSI Design Automation group at IBM T. J. Watson Research Center, Yorktown Heights, NY in 1995, where he manages and leads a research group focused on Physical and Logic Synthesis. He has been working on design and automated synthesis solutions for IBM's high-performance and power-efficient microprocessors and ASICs in advanced CMOS technologies and has received several IBM awards for his work including an IBM Outstanding Technical Achievement award and IBM Execute Now award. He has also been an adjunct assistant professor in the Department of Electrical Engineering at Columbia University, New York where he taught VLSI design and Circuits.
Dr. Puri received 1993 ACM/IEEE Design Automation Scholarship and the 1992 and 1993 Alberta Microelectronics research scholarships for his doctoral research. He has served on program committees of most major VLSI Design Automation conferences, NSF and SRC panels and has been an invited speaker at numerous conferences such as ISSCC, DAC, and ICCAD. He is the inventor of 21 U.S. patents and has authored over 75 publications on the design and synthesis of low-power and high-performance circuits. He currently serves as Associate Editor of IEEE Transactions on Circuits and Systems I and in the past has served as Associate editor of the Transactions on Circuits and Systems II. He serves on ACM SIGDA Physical Design Technical committee. Ruchir was elected an IEEE Fellow in 2006 for contributions to automated logic and physical design of electronic circuits.

Lasse Harju
Dr. Lasse Harju is a SoC architect at ST-Ericsson. His current responsibilities cover SoC system control and power management topics, ranging from low-level circuit technologies to firmware implementations. Dr. Harju earned his PhD degree in 2006 from Tampere University of Technology in Finland. His academic work focused on programmable wireless baseband implementations.

Rudy Lauwereins
Rudy Lauwereins is vice president of imec, which performs world-leading research and delivers industry-relevant technology solutions through global partnerships in nano-electronics, ICT, healthcare and energy. He is responsible for imec’s Smart Systems Technology Office, covering energy efficient green radios, vision systems, (bio)medical and lifestyle electronics as well as wireless autonomous transducer systems and large area organic electronics. He is also a part-time Full Professor at the Katholieke Universiteit Leuven, Belgium, where he teaches Computer Architectures in the Master of Science in Electrotechnical Engineering program.
Before joining imec in 2001, he held a tenure Professorship in the Faculty of Engineering at the Katholieke Universiteit Leuven since 1993. He had obtained a Ph.D. in Electrical Engineering in 1989. Professor Lauwereins has authored and co-authored more than 380 publications in international journals, books and conference proceedings. He is a senior member of the IEEE.

Kees van Berkel
He received an M.Sc. degree (cum laude) in EE from the Delft University of Technology in 1980 and a PhD degree in CS from the Eindhoven University of Technology (TU/e, 1992); is fellow at ST-Ericsson; previously fellow at Philips Research, NXP Research, and ST-NXP Wireless; is a part-time professor in Computing Science at the TU/e since 1996; published about 50 papers, and about 25 patent (applications); pioneered  asynchronous VLSI during the 90’s, published a book on Handshake Circuits, and contributed to their industrial application; co-architected the EVP, a vector DSP for modem and SDR applications, currently in production currently researches  software defined radio, digital wireless communication, multi-core architectures, vector processors, and low power.

Chris Rowen
Dr. Chris Rowen is the founder, chief technical officer, and a member of the board of directors of Tensilica, Inc. He founded Tensilica in July 1997 to develop automatic generation of application-specific microprocessors for high-volume communication and consumer systems. He was a pioneer in the development of RISC architecture at Stanford in the early 1980s and helped start MIPS Computer Systems Inc. in 1984, where he serves in a variety of functions including as vice president for microprocessor development and as the manager for MIPS' European operations. When Silicon Graphics purchased MIPS, he became the technology and market development leader for Silicon Graphics Europe. In 1996, he was hired by Synopsys to be vice president and general manager of the Design Reuse Group. This experience helped him realize the limitations of current microprocessors for embedded design, which led him to the founding of Tensilica. He received a B.A. in physics from Harvard University and M.S. and Ph.D. in electrical engineering from Stanford University. He is well known as a speaker on complex technology and business issues, has authored the book, "Engineering the Complex SOC" (published by Prentice Hall in 2004) and numerous technical articles and conference papers, and he holds over two dozen US and international patents.

Yankin Tanurhan
Dr. Yankin Tanurhan is Vice President of Engineering for DesignWare® ARC Processor Cores and Non-Volatile Memory IP solutions at Synopsys. Before joining Synopsys, Dr. Yankin was Vice President and General Manager of Virage Logic's Processors, SoC Infrastructure and NVM Solutions business units. Prior to this he served as Vice President of Actel's Advanced Applications and System Solutions, where he lead Actel's new architecture design, IP and MPU business units, system and hardware tools and product validation departments. He was also responsible for leading Actel’s embedded FPGA, embedded processor and DSP activities.
Previously, Dr. Yankin served as the director of the department of electronic systems and microsystems of FZI (Forschungszentrum Informatik), and held senior positions at the Institute of Computer Aided Circuit Design and Informatik Forum in Germany, where he lead international hardware/software co-design projects.
 Dr. Yankin has authored more than 100 papers in refereed publications. He holds a B.S. and M.S. in Electrical and Computer Engineering from Rheinisch Westfaellische Technische Hochschule (RWTH) in Aachen, Germany and a Dr. Ing. degree summa cum laude in Electrical Engineering from the University of Karlsruhe (TH) in Karlsruhe, Germany.

Martin Schoeberl
Martin Schoeberl is associate professor at the Technical University of Denmark, at the Department of Informatics and Mathematical Modelling. His research focus is on time-predictable computer architectures and on Java for hard real-time systems. He developed the time-pridictable Java processor JOP and led the research on a chip-multiprocessor version of JOP. This platform was developed within the EU project JEOPARD (Java Environment for Parallel Realtime Development). His current research focus is on time-predictable chip-multiprocessors for hard real-time systems.

Kees Goossens
Kees Goossens received his PhD from the University of Edinburgh in 1993 on hardware verification using embeddings of formal semantics of hardware description languages in proof systems. He worked for Philips/NXP Research from 1995 to 2010 on networks on chip for consumer electronics, where real-time performance and low cost are major constraints. He was part-time full professor at the Delft university of technology from 2007 to 2010, and is currently full professor at the Eindhoven university of technology, where his research focusses on composable (virtualised), predictable (real-time), low-power embedded systems.

Martti Forsell
Martti Forsell is a Chief Research Scientist of Computer Architecture and Parallel Computing at VTT, Oulu, Finland, as well as an Adjunct Professor in the Department of Electrical and Information Engineering at the University of Oulu. He received M.Sc., Ph.Lic., and Ph.D. degrees in computer science from the University of Joensuu, Finland in 1991, 1994, and 1997 respectively. Prior to joining VTT, he has acted as a lecturer, researcher, and acting professor in the Department of Computer Science, University of Joensuu. Dr. Forsell has a long background in parallel and sequential computer architecture and parallel computing research. He is the inventor of the first scalable high-performance CMP architecture armed with an easy-to-use general-purpose parallel application development scheme (consisting of a computational model, programming language, experimental optimizing compiler, and simulation tools) exploiting the PRAM-model, as well as a number of other TLP and ILP architectures, architectural techniques and development methodologies and tools for general purpose computing. At the application-specific front, he has acted as the main architect of the Silicon Hive CSP 2500 processor and programming methodology aimed for low-power digital front-end radio signal processing. He is a co-organizer of the Highly Parallel Processing on a Chip (HPPC) workshop series. His current research interests are processor and computer architectures, chip multi-processors, networks on chip, models of parallel computing, functionality mapping techniques, parallel languages, compilers, simulators, and performance, silicon area and power consumption modeling. He has published 90 scientific publications, holds one patent on processor architectures and programming methodology, and has participated to various research and development projects in cooperation with academia and industry. Recently has has been named as the leader of a large VTT funded project, REPLICA, aiming to remove the performance and programmability limitations of chip multiprocessor architectures with a help of a strong PRAM model of computation.

K. Charles Janac
K. Charles Janac is the Chairman, President and Chief Executive Officer of Arteris Holdings.   Arteris has pioneered the market for Network on Chip (NoC) interconnect IP and Tools for on-chip communications in System on Chip(SoC) type semiconductors. 
 Charlie has over 20 years experience building technology companies.  He started his technology career as employee number two of Cadence Design Systems (originally SDA Inc.), a NYSE traded company.  Subsequently, he served as CEO of HLD Systems, Smart Machines and Nanomix.  Charlie also served as Entrepreneur-in-Residence at Infinity Capital, an early stage venture capital firm in Palo Alto, California and has worked for Exxon Chemical Company in technical and sales positions. 
Born in Prague, Czech Republic, he holds both a B.S. and M.S. degrees in Organic Chemistry from Tufts University and an MBA from Stanford Graduate School of Business.  He holds a patent in polymer film technology.  Charlie, his wife Lydia, and their two children reside in Los Altos Hills, California.

Gerhard P. Fettweis


Marcello Coppola
Marcello Coppola graduated in Computer Science from the University of Pisa, Italy in 1992. He joined the Transputer architecture group in INMOS, Bristol (UK), doing research in multi-core communication together with the key technical people of Transputer technology with special focus on the C104 router. Later, he moved to the Advanced System Technology R&D group of STMicroelectronics, in which started and leaded different research programs. The first one on modeling, completed with SystemC2.0 language definition, OSCI standardization and SystemC deployment within STMicroelectronics. The last one, where he and his team developed the first industrial multiple-die Network-on-Chip called Spidergon STNoC, ended with the deployment company-wide of the technology and first integration in different 32nm multimedia and mobile SoCs. Currently, he is a Director in Home Entertainment & Displays Group, of STMicroelectronics, in Grenoble (France), and he is in charge of the advanced R&D for SoC interconnect, verification and modeling. His research interests include several aspects of design technologies for System-on-Chip, with particular emphasis to modeling, verification, network-on-chip, multi-core architecture and programming models.  He's co-author and/or co-editor of different books and of over 50 technical articles. He is serving or has served as program and/or organizing member in numerous top international conferences and workshops. He has also served as reviewer for international conferences as well as journals and holds a number of patents with both the European and US patent offices.

Pieter van der Wolf
Pieter van der Wolf is a Senior Staff Product Architect at Synopsys. He received his MSc and PhD degrees in Electrical Engineering from Delft University of Technology. He was an Associate Professor at Delft University of Technology before joining Philips Research in 1996. In 2006 he joined NXP Semiconductors when it was spun out of Philips Electronics. In 2009 he joined VirageLogic, which was subsequently acquired by Synopsys. He has worked on a broad range of topics including (multi-) processor architectures and system design methodologies.

Kasahara Hironori
Dr. Hironori Kasahara is a Professor at Department of Computer Science and Engineering and Director of Advanced Multicore Processor Research Institute, Waseda University, Tokyo, Japan and a member of IEEE Computer Society Board of Governors. He received a Ph.D. degree from Waseda University in 1985, and was a visiting scholar in the University of California at Berkeley in 1985, a fulltime assistant professor in 1986, associate professor in 1988 and professor in 1997 at Waseda University. Also, he was a visiting researcher at the University of Illinois at Urbana-Champaign, Center for Supercomputing R&D in 1989-90.
He led several Japanese National Projects such as METI/NEDO Advanced Parallelizing Compiler, Multicore for Real-time Consumer Electronics, Leading Research for Low Power Manycores. He served as a member of MEXT Earth Simulator Architecture Advisory Board, Next Generation Supercomputer Evaluation Committee, High Performance Computing Infrastructure Committee and so on. He published more than 180 reviewed papers, 28 symposium papers, 129 technical reports, 154 Annual Convention Papers with 97 invited talks, 8 patents (25 patent applications) and 400 articles of news papers, TV, magazines, web news and so on. Also, he has served as a PC chair, a PC or a Publication Chair of many conferences supported by IEEE, ACM, IPSJ, such as SC, ICS, ASPLOS, PPoPP, ICPP, IPDPS, ICPADS, CONPAR, JSPP, LCPC and so on. He has received the IFAC World Congress Young Author Prize, the IPSJ Sakai Special Research Award, the Grand Prix runner-up prize at the 2008 LSI of the Year, Best Research Award at the Intel Asia Academic Forum and IEEE Computer Society Golden Core Member. His research interests include parallelizing compilers, multicore and manycore architectures.

Paul Heysters
Dr. Paul M. Heysters is CEO and co-founder of Recore Systems. He has more than 7 years experience working in the field of reconfigurable computing. In his career, he has worked for high-technology companies in both Europe and the USA, including Ericsson, Philips and Chameleon Systems. Before joining Recore Systems, he conducted PhD. research on coarse-grained reconfigurable computing at the University of Twente (The Netherlands) and worked collaboratively with industry organizations.
Paul is coordinator of the EU funded Cutting-edge Reconfigurable ICs for Stream Processing (CRISP) research consortium (www.crisp-project.eu). He is a member of the coordination board of the Sensor Technology Applied in Reconfigurable Systems (STARS) project (www.starsproject.nl). Moreover, he is a board member of the Dutch Shared EDA association.
Paul received his MSc degree in Computer Science from the University of Twente in 1998 and his doctorate in 2004 for his PhD thesis entitled “Coarse-Grained Reconfigurable Processors – Flexibility meets Efficiency.”

Kees Vissers
Kees Vissers graduated from Delft University in the Netherlands. He worked at Philips Research on processors, image processing, HDTV processing and Hardware – Software co-design. He was a visiting industrial fellow at CMU, working on High Level Synthesis, and a visiting industrial fellow at UC Berkeley working on streaming models of computation. He was a director of Architecture at Trimedia, CTO at Chameleon Systems, and consulted for Intel, Nvidia and Xilinx. He is today a distinguished engineer in the CTO office of Xilinx  building teams that work on designing and programming systems that consists of processors and reconfigurable fabric.  He has a quantitative approach to tools and architectures.

Kiyoung Choi
Kiyoung Choi is a professor of the Department of Electrical Engineering and Computer Science, Seoul National University. He received B.S. degree in electronics engineering from Seoul National University in 1978 and M.S. degree in electrical and electronics engineering from KAIST in 1980. He received Ph.D. degree in electrical engineering from Stanford University in 1989. He worked for Cadence Design Systems from 1989 to 1991. His research interests are in computer architecture, embedded systems design, low power design, and design automation.

Ian O'Connor
Ian O'Connor(IEEE S'95-M'98-SM'07, IEE S'87-M'98) is Professor for Heterogeneous and Nanoelectronics Systems Design in the Department of Electronic, Electrical and Control Engineering at Ecole Centrale de Lyon, France. He is currently head of the Heterogeneous Systems Design group at the Lyon Institute of Nanotechnology, of which he is also one of the vice-directors. Since 2008, he also holds a position of Adjunct Professor at Ecole Polytechnique de Montréal, Canada. His research interests include design methods and tools for physically heterogeneous systems on chip, and their application to novel system architectures based on non-conventional devices. He has authored or co-authored over 100 book chapters, journal publications and conference papers and has been workpackage leader or scientific coordinator for several national and European projects. He also serves as an expert with the french Observatory for Micro and Nano Technologies (OMNT), IFIP WG10.5 and Allistene.

Omar Hammami
Omar Hammami is Professor at ENSTA ParisTech/DGA.
His research interests are MPSOC automatic design methodologies (MPSOC synthesis, NOC synthesis), Applied mathematics and optimization for MPSOC, System engineering and embedded systems. He has been involved in numerous research and industrial projects. He is currently involved in 3D IC EDA tools development, 3D Multicore design and Multi-FPGA based Multicore. He is a consultant for several companies and startups involved in multicore SOC EDA and ASIC 2D chip designs.

Kunio Uchiyama
Kunio Uchiyama, Corporate Officer and Chief Scientist of Hitachi, Ltd., received the B.S., M.S. and Ph.D degrees from Tokyo Institute of Technology, Japan. Since 1978 he has been working for the Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan, on design automations, mainframe computers, and microprocessors. He has been leading the research and development of SuperH microprocessors from the beginning of the 1990s. He also serves as a visiting professor of Waseda University. He was awarded by the national Medal of Honor with Purple Ribbon in 2004 for his contribution of high-performance low-power microprocessor development for digital consumer products. 

Pierre Paulin
Dr. Pierre G. Paulin is director of System-on-Chip Platform Automation at STMicroelectronics, Ottawa, Canada. He is responsible for the platform programming tools of a large-scale multi-processor SoC fabric in ST. Previously, he was director of Embedded Systems Technologies for ST in Grenoble, France. Before this, he managed embedded software tools and high-level synthesis R&D with BNR, the research lab of Nortel Networks. His research interests include design automation technologies for multi-processor systems, embedded systems and system-level design. He obtained a Ph.D. from Carleton University, Ottawa, and B.Sc. and M.Sc. degrees from Laval University, Quebec. He won the best presentation award at DAC in 1986, and won the best paper award at ISSS-Codes in 2004. He is a member of the IEEE.

Nakajima Masaitsu
Dr. Masaitsu Nakajima received B.S. degree from Tokyo Institute of Technology in 1985 and joined Matsushita Electric Industrial Co., Ltd., (currently Panasonic Corporation), where He had been working on the development of 64bit RISC and a superscalar processor for parallel computer system, the ASICs for 3DO interactive multi-media player, Panasonic's proprietary 32bit embedded CPU AM33 series CPU core, and IPP, Instruction Parallel Processor, for UniPhier Platform. He received Ph.D. degree from Kobe University in 2007. He is interested in low power and high performance processor architecture, processor implementation, circuit design and design methodology. Currently, he is a general manager of processor core technology group, Digital Core Development Center, Panasonic and he takes responsibility for general purpose CPUs, media processors, low power techniques for UniPhier based SoCs.

Norbert Wehn
Norbert holds the chair for Microlectronic System Design in the department of Electrical Engineering and Information Technology at the University of Kaiserslautern. He has more than 200 publications in various fields of microelectronic system design and holds several patents. He is chairman of the European Design Automation Association, Chairman of the Research Center “Ambient Systems” at TU Kaiserslautern, associate editor of various journals and member of several scientific advisory boards. In 2003 he served as program chair for DATE 2003 and as general chair for DATE 2005 respectively. His special research interests are VLSI-architectures for mobile communication, forward error correction techniques, low-power, advanced SoC architectures and reliability issues in SoC.

Takashi Miyamori
Takashi Miyamori received the B.S. and M.S. degrees in electrical engineering from Keio University, Japan, in 1985 and 1987, respectively. In 1987, he joined Toshiba Corporation, where he was engaged in the research and development of microprocessors. He is currently a Chief Specialist and working on the development of configurable processor cores, media processors,image signal processing processors, and multi-core processors.

Tsuyoshi Isshiki
Tsuyoshi Isshiki has received B.E. and M.E. degrees from Tokyo Institute of Technology in 1990 and 1992, respectively, and received PhD in Computer Engineering from University of California at Santa Cruz in 1996.   He is currently an Associate Professor at Tokyo Institute of Technology, Dept. of Communications and Integrated Systems. His research interests include multimedia SoC designs, Multiprocessor SoC design methodology and its design tools.

Philippe Magarshack
Philippe Magarshack is Technology Group Vice-President and Central CAD & Design Solutions General Manager at STMicroelectronics in Crolles, France. He started his career at AT&T Bell Labs in Murray Hill, NJ, in 1984, as a designer for the first 32bit microprocessor family. In 1989 in joined Thomson-CSF in Grenoble, France, in charge of Military ASIC design methods and libraries. In 1994, he joined the Central R&D group at STMicroelectronics in Crolles, France, where he took several responsibilities in advanced CMOS design platform management. Magarshack now oversees ST's EDA and libraries strategy, enabling products in advanced CMOS and derivatives, and Smart Power.

Bart Kienhuis
Bart Kienhuis, PhD, received a MSEE from Delft University of Technology in 1994 and he received his Ph.D. from Delft University of Technology in 1999. During his Ph.D., he has worked at Philips Research in Eindhoven on a design methodology for high performance video architectures for consumer products. This has resulted in the Y-chart approach and the abstraction pyramid concepts. Both concepts had a clear impact on the embedded system design community. From 1999 until 2000, Bart Kienhuis was a Post Doc in the group of Prof. Edward A. Lee at the University of California at Berkeley, where he worked on the Ptolemy system. At Berkeley, he also started the Compaan project which has lead to an innovated technology behind Compaan Design BV. Bart is the founder and director of Compaan Design. He is also affiliated to Leiden University as an assistant professor in at the Computer Science department. He has served on many technical program committees of leading conference in embedded system design and compilers like CODES, CASES, DATE, EUROPAR, SCOPES.

Joachim Kunkel


Rolf Ernst
Rolf Ernst received a diploma in CS and a Dr.-Ing. in EE from the University of Erlangen-Nuremberg, Germany, in 81 and 87. From 88 to 89, he was with Bell Laboratories, Allentown, PA. Since 90, he has been a professor of electrical engineering at the Technische Universität Braunschweig, Germany, where he chairs a university institute of 65 researchers and staff. He was Head of the Department of Electrical Engineering from 1999 to 2001.
His research activities include embedded system design and design automation. The activities are currently supported by the German "Deutsche Forschungsgemeinschaft" (corresponds to the NSF), by the German BMBF, by the European Union, and by industrial contracts, such as from Intel, Daimler, Ford, Bosch, and Volkswagen. He gave numerous invited presentations and tutorials at major international events and contributed to seminars and summer schools in the areas of hardware/software co-design, embedded system architectures, system modeling and verification.
He is an IEEE Fellow and served as an ACM-SIGDA Distinguished Lecturer. He is a member of the German Academy of Science and Engineering, acatech.  

Frédéric Pétrot
Frédéric Pétrot received the PhD degree in Computer Science from Université Pierre et Marie Curie (Paris VI), Paris, France, in 1994, where has been Assistant Professor in Computer Science until September 2004. From 1989 to 1996, F. Pétrot was one of the main contributors of the open source Alliance VLSI CAD system whose working team received the French Seymour Cray award in 1994. Since 1996, he headed the work on the definition and implementation of the Disydent environment, oriented toward the specification and implementation of multiprocessor SoCs. He joined TIMA in September 2004, and holds a professer position at the Ensimag, Institut Polytechique de Grenoble, France. Since 2007, he heads the System Level Synthesis group of TIMA, where his main focus is the architectural enhancement of MPSoCs and their programming.

Sri Parameswaran
Sri Parameswaran is a Professor in the School of Computer Science and Engineering at the University of New South Wales. He also serves as the Program Director for Computer Engineering. His research interests are in System Level Synthesis, Low power systems, High Level Systems and Network on Chips. He serves on the editorial boards of ACM Transactions on Embedded Computing Systems, the Eurasip Journal on Embedded Systems and the Design Automation of Embedded Systems. He has served on the Program Committees of Design Automation Conference (DAC), Design and Test in Europe (DATE), the International Conference on Computer Aided Design (ICCAD), the International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS), and the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES).

Koichiro Yamashita
Koichiro Yamashita has received the M.E. degrees in computer science from Waseda University, and joined Fujitsu LTD in 1995. He had worked for parallel operating system on the vector-parallel super computing system (VPP series) for 5 years, and moved to electric device group (EDG) of Fujitsu LTD in 2001. In 2006, he moved to Fujitsu Laboratories. In 2009, he works as manager of mobile phone BU of Fujitsu LTD and senior researcher of platform technology labs of Fujitsu Laboratories concurrently. In 2009, he assumed the position of the chairman of SMP Working Group of Symbian Foundation.