TU Munich, Germany
Smart Cache Eviction Policies for NoC-centric MPSoCs
The Memory Wall has been and remains an omnipresent challenge for the performance efficiency of multi-/many-core processing platforms for the last 15 years, at least. The Memory Wall manifests in various forms and affects different system parameters: examples are insufficient memory capacity to store large amounts of data local to the processing units, access interference on shared memory controllers, insufficient streaming or alternating read/write cycle bandwidth, and cache coherency protocol implementations, which lead to additional latencies. The power/energy implications resulting from the mentioned issues often are more severe than the associated performance degradation. In the past two MPSOC Forum events we reported on our work on region-based cache coherence and near memory acceleration on tile-based MPSoC architectures. This year, we want to introduce an advanced cache eviction policy specifically optimized for such tile- and 2D-mesh-NoC-based MPSOCs. In multi-core systems with potentially multiple sharers of the same data, caches need to be kept coherent to maintain application correctness. Cache coherence for large NoC-centric many-core systems is provisioned using a directory structure which holds metadata on sharers. Directory-based coherence was introduced 1990 by the Stanford DASH multiprocessor project. They optimized the directory depth by implementing a cache-like structure they call sparse directories. Owing to conflict and capacity limitations, sparse directories, like caches, desirably utilize replacement policies that retain those sharer metadata, which results in fewest future replacements or evictions, thus optimizing the application execution time. In this talk, we present results of an advanced hybrid sparse directory and a cache replacement policy that outperforms established best practice policies like least-recently used (LRU), least-frequently used (LFU) or shortest distance (SD). The goal is to come as close as possible to the (unattainable) Bélády optimum. This work is supported by the German Research Foundation (DFG) under the grant number 146371743 – TRR89: Invasive Computing.
Andreas Herkersdorf is a professor in the Department of Electrical and Computer Engineering and also adjunct to the Department of Informatics at Technical University of Munich (TUM). He received the Dipl.-Ing. degree from TUM in 1987 and the Dr. degree from ETH Zurich, Switzerland, in 1991, both in electrical engineering. Between 1988 and 2003, he has been in technical and management positions with the IBM Research Laboratory in Rueschlikon, Switzerland.
Since 2003, Dr. Herkersdorf is director of the Chair for Integrated Systems at TUM. He is a senior member of the IEEE, member of the DFG (German Research Foundation) Review Board and serves as editor for Springer and Elsevier journals for design automation and communications electronics. His research interests include application-specific multi-processor architectures, IP network processing, Network on Chip, system level SoC modeling and design space exploration methods, and self-adaptive fault-tolerant computing.
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