Fumio Arakawa

The University of Tokyo, Japan

Edge-AI accelerator in 2-nm Technology

Abstract

We are developing an edge-AI accelerator in 2-nm Technology. The members of the developing project are Leading-edge Semiconductor Technology Center (LSTC) and Tenstorrent inc., and the LSTC members are the National Institute of Advanced Industrial Science and Technology (AIST), Rapidus Corporation., and the University of Tokyo. I’ll introduce our approach to enhance the power efficiency of the accelerator five-times higher than a leading-edge accelerator when we plan the project. Our architecture reduces memory footprints required to sustain typical AI processing like Transformer with a large language model (LLM), and makes the accelerator efficient.

Biography

Fumio Arakawa is a designated researcher of d.lab at the University of Tokyo, and an invited professor of Graduate School of Informatics at Nagoya University. His research interests include architecture and micro-architecture of low-power and high-performance processors. He has founded an R&D and consulting company, Famer Systems, Inc. to contribute to industries with his R&D experience of Hitachi and Renesas Electronics. He is the organizing committee chair of the Cool Chips conference series. He served as a Guest Editor of IEEE Micro for seven times, and TPC members of conferences including ISSCC, VLSI Circuits Symposium, A-SSCC, and MCSoC. He has a Ph.D. in electrical engineering from the University of Tokyo. He is a member of IEEE and IEICE.