Tajana Simunic Rosing

UCSD, USA

Hyperdimensional Computing and Applications

Abstract

In today’s world technological advances are continually creating more data than what we can cope with. Much of data processing will need to run at least partly on devices at the edge. However, running existing machine learning on such systems would drain their batteries and be too slow.  Hyperdimensional (HD) computing is a class of learning algorithms that is motivated by the observation that the human brain operates on a lot of simple data in parallel. Systems that use HD computing to learn can run directly in memory and have been shown to be accurate, fast and very energy efficient.  In this talk I will present some of my team’s recent work on HD computing software and hardware infrastructure, including novel algorithms & tapped out hardware accelerators supporting learning on multimodal, complex and large data.  Current results indicate that HD computing can provide state of the art accuracy on 100s of GB & TB of data, at much higher energy efficiency and speed than the state of the art.

Biography

Tajana Šimunić Rosing is a Fratamico Endowed Chair of Computer Science and Engineering and Electrical Engineering, a director of SRC and DARPA funded $56.5M PRISM Center and the System Energy Efficiency Lab at UCSD. She is also an ACM & IEEE Fellow, and was selected as Semiconductor Industry Association’s University Research Award winner for Design in 2022. Her research interests are in energy efficient computing, computer architecture, neuromorphic computing, distributed and embedded systems. She was funded by SRC as a graduate student, and has been involved as a PI and Theme lead in GSRC, MuSyC, TerraSwarm, CRISP, is currently a PI in CoCoSys Center, and leads the PRISM Center. She is also leading a number of DARPA, NSF and SRC funded projects related to HD Computing, SRC funded project acceleration of 3rd generation Fully Homomorphic Encryption, and NSF AI TILOS Research Institute projects on federated learning and AI-based chip design. From 1998 until 2005 she was a full time research scientist at HP Labs while also leading research efforts at Stanford University. She finished her PhD in EE in 2001 at Stanford, concurrently with finishing her Masters in Engineering Management. Prior to pursuing the PhD, she worked as a senior design engineer at Intel for 4 years.

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