Tsuyoshi Isshiki

Institute of Science Tokyo, Japan

RISC-V AI Accelerator Design Platform on C2RTL System Design Verification Framework

Abstract

In this talk, we introduce our recent results on RISC-V HW/SW System Design Platform our C++ based system design framework (C2RTL)
with a number of successful chip designs on 28nm and 12nm CMOS on AI accelerators and IoT devices. Building upon this system design platform,
we are now preparing the next project phase of establishing the RISC-V AI Accelerator Design Platform, encompassing numerous AI/analytics application acceleration.
We show our preliminary PPA (Power/Performace/Area) analysis of Llama3-8B with comparisons with existing state-of-the-art hardware platforms,
identifying potential opportunities for drastic energy-efficient solutions.

Biography

Tsuyoshi Isshiki has received B.E. and M.E. degrees from Tokyo Institute of Technology in 1990 and 1992, respectively, and received PhD in Computer Engineering from University of California at Santa Cruz in 1996.  He is currently a professor at Institute of Science Tokyo, Dept. Information and Communications Engineering. His research interests include multimedia SoC designs and RISC-V SoC design methodologies and tools.

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