Tsuyoshi Isshiki

Institute of Science Tokyo, Japan

RISC-V LLM Accelerator Design Platform on C2RTL System Design Verification Framework

Abstract

In this talk, we introduce our on-going LLM accelerator embedded RISC-V development on our C++ based system design framework (C2RTL).
Our customizable RISC-V architecture fully described in C++ consists of HW accelerator interface between the RISC-V pipeline, allowing easy integration of custom instructions (data transfer, compute, control, etc) and fine-grain control of the highly-parallel custom compute fabric and high-bandwidth custom
memory subsystem. Custom instructions designed for LLM acceleration consists of tensor-level data transfers (weight matrix, KV-cache), matmul (matrix
multiplication) compute, and special functions (RMS-norm, SoftMax, Swiglu), enabling an easy SW generation from common LLM framework such as Hugging Face.

Biography

Tsuyoshi Isshiki has received B.E. and M.E. degrees from Tokyo Institute of Technology in 1990 and 1992, respectively, and received PhD in Computer Engineering from University of California at Santa Cruz in 1996.
He is currently a professor at Institute of Science Tokyo, Dept. Information and Communications Engineering. His research interests include multimedia SoC designs and RISC-V SoC design methodologies and tools.

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