Tohru Ishihara

Nagoya University, Japan

A Cell-based DRAM for Fully Synthesizable PiM Accelerator Design

Abstract

In modern VLSI designs, the cost and energy consumption of data movement between processors and memory components often dominate the computation itself. Near-memory computing and Processing-in-Memory (PiM) architectures have thus attracted a lot of attention as solutions to addressing the data movement issue. In this talk, we first introduce a cell-based DRAM where the two-transistor (2T) Gain Cell structure is adopted as the bit cell storage with a specifically designed circuit structure to enable near-threshold voltage operation. The cell-based DRAM structure allows commercial automatic place and route (APR) tools to place and route the memory blocks and the functional units in a mixed manner, thus achieving fully synthesizable PiM with much higher bandwidth than traditional approaches. The experimental results show that the design strategy using the proposed cell-based DRAM is APR-friendly with commercial tools and can operate at a supply voltage as low as 0.4 V while outperforming conventional memories in terms of area cost (up to 3.8x smaller) and energy consumption (up to 13.2x lower).

Biography

Tohru Ishihara received his Dr.Eng. degree in computer science from Kyushu University in 2000. For the next three years, he was a Research Associate in the University of Tokyo. From 2003 to 2005, he was with Fujitsu Laboratories of America as a Research Staff of an Advanced CAD Technology Group. From 2005 to 2011, he was with Kyushu University as an Associate Professor. For the next seven years he was with Kyoto University. In October 2018, he joined Nagoya University where he is currently a Professor in the Department of Computing and Software Systems. His research interests include low-power design methodologies and power management techniques for embedded systems. Dr. Ishihara is a member of the IEEE, ACM, IPSJ and IEICE.

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