K. Charles Janac
Arteris Inc., USA
Assembling Large-Scale, Cache Coherent SoCs
SoCs have become entire electronic systems with many functions such as data processing, machine learning, vision acceleration and wireless communications running on board simultaneously. Examples include automotive ADAS SoCs, data center machine learning accelerators, and network Edge SoCs. Such large, complex SoCs require support for a variety of cache coherent and non-coherent data traffic classes as well as efficient connections to processors, memory subsystems, cache coherent accelerators, and even chiplets. This presentation describes a novel “Ncore 3” cache coherent interconnect that supports multiple concurrent cache coherent protocols and can be used in “tiled” implementations to efficiently assemble large scale, distributed cache coherent systems comprising hundreds of coherent agents.
Charles Janac is the President, Chief Executive Officer and Chairman of Arteris IP. Since 2006, Arteris has pioneered the market for Network on Chip (NoC) interconnect IP for communications inside semiconductor chips. Arteris IP products are designed into semiconductor chips used in majority of production automated driving assist (ADAS) car electronics, Machine Learning SoCs as well as latest 5G smart phones.
Charlie started his technology career as employee number two of Cadence Design Systems (originally SDA Inc.), a publicly traded EDA software company. Subsequently, he served as Chief Executive of HLD Systems, Smart Machines and Nanomix. Charlie also served as Entrepreneur-in-Residence at Infinity Capital, an early stage venture capital firm.
He holds both a B.S. and M.S. degrees in Organic Chemistry from Tufts University and an MBA from Stanford Graduate School of Business.
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