Gerhard P. Fettweis

TU Dresden, Germany

A Novel MPSoC Memory Access Optimization

Abstract

MPSoCs contain many processing elements (PEs) which, e.g. due to clustering, share a common on-chip memory. This allows for easier hand-off of data bocks from one PE to the other, as well as minimizes on-chip memory area. However, sharing memory incurs runtime conflicts, which entail performance and power penalties. To ease this restriction, we introduce a novel method for memory Access Interval Prediction. It minimizes conflicts by predicting the interval between two consecutive memory accesses. In contrast to state-of-art, we do not rely on compile time information or other a priori knowledge. Standard benchmarks show that we can predict over 80 percent of all memory access intervals correctly, thereby significantly reducing the number of access conflicts.

This work has been mainly carried out by Robert Wittig, with the help of Emil Matus and Gerhard Fettweis.

Biography

Gerhard P. Fettweis, earned a Ph.D. under H. Meyr at RWTH Aachen. After a postdoc at IBM Research, San Jose, he joined TCSI, Berkeley. Since 1994 he is Vodafone Chair Professor at TU Dresden. Since 2018 he also heads the Barkhausen Institute. 2019 he was elected into the DFG Senate. He researches wireless transmission and chip design, and coordinates e.g. the 5GLab Germany, has spun-out 17 startups, and is member of 2 German Academies: Academy of Sciences/“Leopoldina”, Academy of Engineering/“acatech”.