Philippe Flatresse
Dolphin Design, Meylan, France
Biography
Philippe Flatresse (philippe.flatresse@soitec.com) received his Ph.D. degree in microlectronics in 1999 from the Institut National Polytechnique de Grenoble, France. During his thesis work, he developed the LETISOI spice model dedicated to silicon-on-insulator (SOI) technologies at CEA LETI, Grenoble, France. In 2000, he joined the STMicroelectronics research and development center, Crolles, France, to deploy SOI digital designs. He pioneered the partially and fully depleted SOI (FD-SOI) technologies and demonstrated their key advantages for low-power, high-performance digital applications. As a design architect, he contributed to the development of products targeting high-growth areas, such as advanced driver assistance system, microcontroller unit, and Internet of Things applications. He was in charge of exploring the energy-efficiency limits on multicore systems for ultralow-power processing by combining FD-SOI technology with body biasing and advanced low-power techniques. He recently joined the Soitec business development team as an expert in digital applications to participate to the worldwide deployment of FD-SOI technologies.
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