Tsuyoshi Isshiki

Tokyo Institute of Technology, Japan

RISC-V System Design Platform on C2RTL System-Level Design Verification Framework

Abstract

In this talk, we introduce our recent works on RISC-V System Design Platform using our C++-based system design framework (C2RTL). Our C++ RISC-V core model offers wide range of ISA/memory configurations (32/64-bits, full range of IMAFD ISA subsets, cache/MMUs, AXI4 master ports, etc) from a single set of C++ sources, as well as the entire SoC models including AXI4 bus system and slave peripherals. This C++ RISC-V SoC model directly serves as fast system-level SoC simulator as well as the source for auto-generated RTL and cycle-accurate simulator of the SoC using our C2RTL framework. We plan to utilize our RISC-V Platform to application-specific extensions and custom accelerators for drastically improving throughput/power efficiency.

Biography

Tsuyoshi Isshiki has received B.E. and M.E. degrees from Tokyo Institute of Technology in 1990 and 1992, respectively, and received PhD in Computer Engineering from University of California at Santa Cruz in 1996. He is currently a professor at Tokyo Institute of Technology, Dept. Information and Communications Engineering. His research interests include multimedia SoC designs and RISC-V SoC design methodologies and tools.