Yiran Chen

Duke University, USA

Big AI for Small Devices

Abstract

As artificial intelligence (AI) transforms industries, state-of-the-art models have exploded in size and capability. However, deploying these models on resource-constrained edge devices remains a significant challenge. These devices face stringent limitations in compute, memory, power, and communication, creating a gap between the demands of advanced AI models and the capabilities of edge hardware—hindering the widespread deployment of intelligence. In this talk, we will re-examine techniques for bridging this gap and bring large-scale AI to small devices. We will begin by discussing model compression techniques, including pruning and quantization, with an emphasis on aligning them with the architectural characteristics of edge hardware. We will then expand our focus to collaborative edge AI systems, exploring methods to reduce both inference and training costs in distributed settings. Finally, we will delve into the underlying design philosophies and their evolution toward the next generation of edge computing systems.

Biography

Yiran Chen is the John Cocke Distinguished Professor of Electrical and Computer Engineering at Duke University. He serves as the Principal Investigator and Director of the NSF AI Institute for Edge Computing – Athena, the NSF Industry–University Cooperative Research Center (IUCRC) for Alternative Sustainable and Intelligent Computing (ASIC), and Co-Director of the Duke Center for Computational Evolutionary Intelligence (DCEI). Dr. Chen has authored over 600 publications and holds 96 U.S. patents. His work has received widespread recognition, including two Test-of-Time Awards and 13 Best Paper/Poster Awards. He is the recipient of the IEEE Circuits and Systems Society’s Charles A. Desoer Technical Achievement Award and the IEEE Computer Society’s Edward J. McCluskey Technical Achievement Award. Dr. Chen is a Fellow of the AAAS, ACM, IEEE, and NAI. He also serves as the inaugural Editor-in-Chief of IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCASAI) and the founding Chair of the IEEE Circuits and Systems Society’s Machine Learning Circuits and Systems (MLCAS) Technical Committee.