NEC Corp., Japan
Simulated Annealing on a vector processor
Combinational optimization methods are effective to solve various social problems. There are many methods to solve combinational optimization problems, however, specialized algorithms can solve with high quality, but, require long preparation time. A quantum computing/annealing can solve various combinational problems with short preparation time.
A simulated annealing does not needs long preparation time, but its quality of solutions would not be good and it takes long computational time.
To enhance the quality of solutions of simulated annealing method, continuous trials is necessary. NEC’s vector processor can help efficient continuous trials of simulated annealing, since it has huge vector registers and huge memory band width. In this talk, advantages of simulated annealing on the vector processor is presented.
Yuichi Nakamura received his B.E. degree in information engineering and M.E. degree in electrical engineering from the Tokyo Institute of Technology in 1986 and 1988, respectively. He received his PhD. from the Graduate School of Information, Production and Systems, Waseda University, in 2007. He joined NEC Corp. in 1988 and he is currently he is currently a vice president at NEC Corp. He is also a guest professor of National Institute of Informatics and Waseda and Tokyo University. He has more than 25 years of professional experience in electronic design automation, signal processing, network on chip and quantum computing.
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